Welcome to the future of embedded real-time computing
From tiny multi-core microcontrollers (MCU) all the way up to many-core exascale class chips

The patent pending SSRT technology suite will deliver superior timing predictability with market-leading real-time performance:

  1. Existing 1, 2 and 3 core designs may transition to SSRT ≤ 16 core MCU technologies to dramatically increase real-time computing power to deliver new cyber-physical capabilities
  2. Existing single-core designs may transition to SSRT technologies to improve the real-time properties of the system, increase safety, simplify certification, and reduce expensive run-time failures in the field
  3. Existing designs distributed over 2 to 3 MCU may transition to SSRT multi-core technologies to reduce costs without sacrificing reliability or performance
  4. Most developers will select SSRT technologies to win all these gains at the same time!

Each technology can be used separately, or coupled together, to manage the most demanding hard real-time, mixed criticality and peripheral management problems. 

The SSRT technologies can be combined with unmodiifed COTS chip components to create a de-facto standard computer architecture that is suitable for use in all cyber-physical systems, for all approaches to real-time software (event-driven, time-driven, ...) and in all sectors (automotive, aviation, ...).

Learn more about each of the SSRT technologies in the slideshows below.  Find a technical chart comparing capabilities at the bottom of this page.

"AbsInt is a leading vendor of Worst Case Execution Time (WCET) analysis tools. ... I consider the SRQ-to-M design contributions would be very helpful to basically all projects who plan to run critical real-time software on multi-cores.  AbsInt is interested to explore participation in any project to advance the SRQ-to-M design." 

    Dr.-Ing. Christian Ferdinand (CEO AbsInt)  More...

"AdaCore is a leading provider of commercial software solutions for Ada, a state-of-the-art programming language designed for large, long-lived applications where safety, security, and reliability are critical. ... the innovative capacity offered by SRQ-to-M to run hard real-time tasks, soft real-time and general purpose tasks concurrently on multi cores offers significant performance improvements.  Much more computing can be done in parallel. ... In summary, it is clear that achieving improved real-time predictability, parallelism and performance are highly desireable objectives that the real-time market will appreciate.  In these regards, SRQ-to-M is a very interesting and innovative architecture.  AdaCore is interested to explore participation in any project to advance the SRQ-to-M design." 

    Dr. José F. Ruiz (Senior Software Engineer, AdaCore)  More...

What is SSRT?

The SSRT: Computing and Peripheral family is the answer to published top priority Government and industry needs for high performance real-time capable multi-core (and many-core) computers, on which both general purpose and real-time software run concurrently, efficiently and is easy to write, verify, certify and maintain.  SRRT eliminates or controls problems at the source, in the hardware, making everybodies lives simpler and safer.

Transforming Hardware

Add the small SSRT modules to increase the functionality, efficiency, safety, security, and determinism of your preferred (vendor neutral) COTS multi-core chip architecture.  SSRT will increase overall system performance and reduce total cost of ownership in a vast range of safety, security and mixed criticality applications for a very wide range of industries.  Some SSRT technologies deliver their benefits with excellent performance in FPGA.

Easy to Support

Extensive consultation with experts from the entire industry vertical during the design phase ensures that existing RTOS, embedded hypervisors, and third party applications are easily supported on SSRT enhanced products.

The elimination/control of timing interference delivers increased determinism and reliability that benefits the entire industry vertical and will reduce NRE and after sales service costs. 

  • Safe and Secure Real-time: Agile Peripherals with Robust Partitioning (SSRT: APRP)

    Project: SSRT: Agile Peripherals with Robust Partitioning Overview

    The patent pending SSRT: APRP technologies enable third-party chip designers to quickly and easily create statically time analyzable, multi-/many-core computer (subsystems) that are optimised for the agile management of peripherals (sensor, actuators, networks).  SSRT: APRP designs are fast in FPGA (and ASIC) and employ unmodified (vendor neutral) COTS CPU, cache, NoC, memory, and peripheral modules.

    Each SSRT: APRP cluster enables the concurrent (statically time-analyzable) operation of ≤ 80 bus masters (on one chip) in a way that guarantees high-bandwidth, low latency, low jitter access (for each and every bus master) to a shared memory subsystem capable of sustaining over >500 gigabit/s throughput (@ 200 MHz).  Every clock-cycle:

    • all ≤ 16 processor cores  can concurrently run a different hard real-time task;
    • each of those hard real-time tasks can concurrently access any 1 of ≤ 64 bus slave peripherals and/or shared on-chip memories with excellent performance; and
    • all ≤ 64 bus master peripherals can concurrently access shared on-chip memories at any time.

    SSRT: APRP is not a mesh- or ring-based network on chip (NoC) technology, althought it can be connected to those on-chip networks where desirable SSRT: APRP is suitable for use in FPGA and ASIC, and in microcontrollers through to server grade processors.  Supports ≥ 2 SSRT: APRP clusters per ASIC chip.  The project is currently entering the industry consultation phase.  Enquiries are welcome.  Commercial implementations for FPGA could be available in the near term with very low development effort, e.g. for ARM processors.


  • Dedicated memory subsystem optimised for managing peripherals

    SSRT: Agile Peripherals with Robust Partitioning has been explicitly designed to meet the demanding real-time, safety, security, and (re)certification needs of automotive, aviation, aerospace and defence, industrial controllers, and robotics applications.

    SSRT: APRP revolves around the use of a very high bandwidth (>500 gigabit/s aggregate bandwidth @ 200 MHz), low latency, statically time-analyzable, on-chip memory subsystem to:

    • dramatically increase the total amount of random access memory bandwidth within a single chip;
    • dramatically increase the amount of (multi-core) computing power that can be applied (in a statically time-analyzable way) to manage all types of (latency sensitive, bulk-data, ...) peripherals; 
    • ensure that the peripherals have sufficient memory bandwidth to operate at wire-speeds;
    • significantly decrease the use of off-chip memory bandwith by peripherals to accelerate computationally/memory intensive tasks running on other cores.

    SSRT: APRP works with unmodified (vendor neutral) COTS CPU, cache, NoC, memory, and peripheral modules.
    SSRT: APRP can also be coupled with SSRT: Q2M and/or SSRT: Revolution.

  • All cores, all peripherals, all statically time analyzable, all the time


    SSRT: APRP employs robust partitioning:

    • ≤ 64 "single bus slave peripheral equivalent" partitions;
    • ≤ 64 "single bus master peripheral equivalent" (SBMPE) partitions;
      • supports DMA transfers to and from peripherals in the usual way;
    • ≤ 16 "single core equivalent" (SCE) partitions;
      • each core can access all 64 bus slave peripheral partitions;
      • each core can access shared memory directly in the usual way;

    Each and every partition:

    • has strictly enforced bandwidth, latency and jitter guarantees;
    • has robust time and space partitioning from every other unrelated partition, including isolation from (babbling) faults;
    • optionally eliminates covert timing channels between it and every other unrelated partition;
    • has guaranteed memory bandwidth and strictly upper-bound latency and jitter assurances;
    • is fully time composable; and
    • can be statically time analysed in isolation using COTS static WCET analysis tools.

    Each partition in a SSRT: APRP cluster is configured with the most appropriate memory access latency, and bandwidth guarantees to maximise system performance.  For example, low-bandwidth bus-master peripherals are configured with sufficient bandwidth to permit wire-speed operation, but are configured with less bandwidth than the processor cores servicing those peripherals. 

  • Simplify multi-core task scheduling and reduce preemption costs

    SSRT: APRP supports ≤ 16 "single core equivalent" (SCE) partitions, in which each SCE partition can:

    • be granted access to any one of the 64 bus slave peripherals;
    • access any of it's assigned bus slave peripherals with low latency and low jitter;
    • access shared peripheral memory with low latency and low jitter;

    SSRT: APRP's robust partitioning permits:

    • mixing and matching static "time and space" task schedulers with dynamic task schedulers;
    • scheduling tasks at different rates on each core;
    • minimising pre-emption by assigning long duration tasks to one or more cores, and high-frequency and/or short duration tasks to one or more other cores;
    • assigning the management of peripherals to different cores by event frequency, event duration, functional grouping, ...

    This all greatly simplifies the management of peripheral events with conflicting scheduling requirements.

  • SSRT: APRP vs. Network On Chips


    Each SSRT: Agile Peripherals with Robust Partitioning cluster employs a high-bandwidth, statically time-analysable interconnect that integrates a tightly coupled on-chip shared memory subsystem as the primary means for inter-device communication.  SSRT: APRP is explicitly optimised to manage intra- and inter-core messaging, core-to-peripheral control, peripheral-to-core messaging, peripheral-to-peripheral messaging, inter- and intra-core shared memory (for sharing access to both run-time data and executable code) as well as scratch pad memory in an holistic integrated manner.

    In contrast, almost all modern computer architectures (including the latest published real-time architecture proposals) focus exclusively on a Bus or Network on Chip interconnect as their primary means of inter-device communication.  Example interconnects that do not employ integrated memory stores include, but are not limited to: layered busses, two dimensional bidirectional torus meshes, and dual-ring networks.  In these designs processor cores, on-chip memories, network interfaces, sensors and actuators are all seen as leaf nodes that are attached to the memoryless interconnect.  In these designs the various types of operations performed by a computer are all implemented as messages that are transmitted over the top of the interconnect, removing the opportunity for intelligent system level performance optimisation.  For example, reception of network packets may be inefficiently handled.

    SSRT: Agile Peripherals with Robust Partitioning is not only simpler than most modern (memoryless) NoC interconnects, but it can achieve higher exploitable bandwidth, lower latency, increase total exploitable memory bandwidth on chip, improve power efficiency, simplify software development, and make more efficient utilisation of on-chip memory.  These and other benefits make SSRT: APRP a far more viable solution to resolve the challenges that currently prevent the shift to true mixed criticality systems.


  • Safe and Secure Real-time: Quick to Market (SSRT: Q2M)Project: SR-Q2M Overview

    The low circuit area, patent pending, SSRT: Q2M technologies enable the creation of multi-core real-time computers (that predominantly use SDRAM/FLASH) using unmodified (vendor neutral) COTS CPU, cache, NoC, memory, and peripheral modules.  It supports heterogeneous CPU designs like ARM's BigLittle architecture and efficiently enables the CONCURRENT execution of hard real-time and general purpose (ACET) tasks.  It supports:

    • high performance sharing of ≤ 4 on/off chip SDRAM/FLASH memory channels;
    • ≤ 4 heterogenous processor cores (with cache) per memory channel:
      • 1 statically time analysable core optimised for real-time performance;
      • ≤ 3 cores optimised for fast general-purpose performance;
    • Precisely regulates the worst-case-execution time of a real-time task that accesses a shared memory channel, permitting all other bus-masters to utilise all remaining bandwidth of that memory channel to increase overall system performance.  
      • e.g. Regulate the execution time of a hard real-time task so that it run at 90% of it's peak single-core performance while enabling other cores and peripherals to opportunistically utilise all remaining memory bandwidth.
      • Achieves far superior system performance when compared with time-slot based "Memory Wheels".  
    • Provides easy multi-core upgrade path for the most demanding single-core hard real-time / safety designs;
    • SSRT: Q2M prototype demonstrated a ≤ 4x increase in computing power when upgrading (a cacheless, hard real-time suitable) single core design to dual core design by adding 1 core with cache for concurrently running non-real time task(s); and
    • Easily coupled with SSRT: APRP to increase peripheral and system performance.

  • Do more work with same size/weight & less cost

    SSRT: Q2M is a small circuit designed to provide enhanced real-time capabilities for otherwise UNMODIFIED globally deployed COTS general purpose chip architectures.  

    SSRT: Q2M will enable pin-for-pin replacement of current (real-time suitable) single-core chips with a secure real-time multi-core architecture using the SAME processor core and development tools.

    End-users will gain increased functionality and computing power with more efficient energy consumption, without increasing component size, weight, or the bill of material count and design verification complexity.

    New commercial functionality can be quickly added at design time while reducing engineering costs to increase profits.  Couple SSRT: Q2M with SSRT: APRP to achieve peak peripheral performance and free up more memory bandwidth for software tasks.

  • Complete all tasks fast!

    SSRT: Q2M is a high performance multi-core design optimised to CONCURRENTLY run and satisfy both average case execution time (ACET) and worst case execution time (WCET) tasks and performance goals.  SSRT: Q2M permits all cores to be running tasks at all times. SSRT: Q2M supports the use of heterogeneous CPUs such as the ARM BigLittle.  It also permits the memory subsystem to be optimised to meet the needs of the currently active set of tasks.

    Complete real-time tasks fast!

    Today:  a real-time task in a multi-core enviornment can slow down by up to 20x.  In contrast,  SSRT: Q2M enables hard real-time tasks to achieve near single-core performance and predictability, while enabling other cores / peripherals to run concurrently to increae total system performance.   All hard real-time tasks are run within a "single-core equivalent" context that is highly optimised for servicing real-time tasks with excellent performance.  SSRT: Q2M regulates the worst case execution time of the software, ensuring sufficient SDRAM/FLASH memory bandwidth is made available to the real-time task so it can meet the most demanding deadlines, with all other memory bandwidth supplied to other bus master devices.  Couple SSRT: Q2M with SSRT: APRP  to minimize peripheral access to SDRAM, minimize preemption, and improve overall system performance.   

    Complete non real-time tasks fast!

    Non real-time tasks are run on processor and memory subsystems optimised for fast-per-task execution, free from the constraints of time analyzability requirements.  Out of order execution processors can be used while hard real-time tasks are executing on other (time analysable) cores.  SSRT: Q2M ensures constant availability of memory bandwidth, ensuring cache-misses are regularly serviced and peripherals can write into main memory.   

  • Industry Consultations During the Design of SSRT: Q2M

    At milestones in the SSRT: Q2M design life-cycle, Synaptic Laboratories consulted and sought feedback from world leading experts in global companies and research institutions including partners and advisors to relevant major EU research projects.  
    These experts represented the entire relevant ecosystem vertical, including hardware and software design, global real-time operating system (RTOS) vendors, worst-case execution time (WCET) analysis tool vendors, a leading programming language vendor and end users of safety-critical systems:

    • AbsInt GmbH                                   Germany        (global WCET analysis tool vendor)
    • AdaCoreInc.                                  USA & France   (global: real-time development tools) 
    • Clemson University                         USA                (chip design experts)
    • École Polytechnique de Montréal  Canada           (real-time expert, formerly European Space Agency staff)
    • Green Hills Software                       Global            (global: world’s most highly certified Real-time Operating System)
    • OAR Corporation                             USA                (globally deployed:  RTEMS RTOS)
    • Thales Defense and Space
    • Tidorum                                           EU                 (WCET analysis)
    • Intel's Wind River                   Global             (Real-time Operating System)
  • Results of performance analysis on SSRT: Q2M prototype

    1. The presence of SSRT: Q2M has negligible negative impact on the general purpose performance of the COTS architecture.
    2. The SSRT: Q2M design principles are sound and the prototype is fundamentally correct.
    3. SSRT: Q2M delivers near-deterministic high-performance execution of hard/soft real-time tasks while also maintaining excellent performance for competing general purpose tasks (average case execution time ACET), with all cores active, under all tested configurations. 
    4. Specifically SSRT: Q2M (with instruction and data caches enabled) achieves near-deterministic execution of a (non-preempted) hard real-time task when competing against memory access patterns that may be unknown or unpredictable at run-time.  Consequently, it is reasonable to conclude that SSRT: Q2M will enable the static and behavioral WCET analysis of hard real-time tasks in a multi-core system with all cores active.  Only a trivially simple transformation on the output of today's commercially available WCET analysis tools is required. 
    5. SSRT: Q2M unlocks up to 4x more peak computing power in mixed criticality hard real-time applications in quad-core configurations (scales up to 16 cores).

  • Safe and Secure Real-time: Revolution (SSRT: Revolution)330x230

    SSRT: Revolution supports:

    • 1000's of concurrent hard real-time tasks
    • Massive memory and on-chip network bandwidth
    • Clock cycle deterministic behavior of all circuitry
    • Designed to tweak server grade processors and couple them with ≤1000 time-analyzable, power efficient cores to deliver unprecedented high-assurance, energy-efficient, safety-critical, cyber-physical and mixed criticality capabilities
    • Employs 1 or more SSRT: APRP clusters for managing peripherals


  • Safe and Secure Real-time: Revolution (SSRT: Revolution)330x230

    More information about the capabilities targeted in the SSRT: Revolution project can be found in the fourth slide show (below) entitled "Common Features"

    Also see extensive information in the technical comparison chart below.

  • Common features found across the Safe and Secure Real-Time family420x230

    The SSRT family target a common set of goals:

    • No (or minimal) changes to existing third party hardware
      • Vendor neutral
    • No (or minimal) changes to existing third party software
      • RTOS vendor neutral
    • All real-time tasks are statically time analyzable
      • Also supports measurement based WCET analysis
    • Designed to satisfy real-time, safety and security requirements


    Click on one of the tabs to learn about how SSRT supports specific goals.

  • The SSRT family targets many large markets

    The SSRT: family of technologies have extremely broad global market applications because it they are suitable for use with all mainstream CPU instruction sets, and can be adapted to support all embedded COTS hardware IP (CPU cores, network on chip, peripherals, etc).

    The SSRT family of technologies is well suited for safety and security systems, cyber-physical systems, critical real-time embedded systems, and more:

    All high assurance SAFETY systems, including:                  
    All high-assurance SECURITY systems, including: 
    • aerospace and defence
    • aviation
    • automotive
    • critical infrastructure
    • robotics
    • industrial control
    • Internet of Things (CISCO: 50 billion devices 2020)
    • medical
    • etc.
    • aerospace and defence
    • critical infrastructure
    • banking
    • medical
    • mobile phones
    • etc.
  • An Example Market: Critical Real-time Embedded Systems (CRTES)


    The features delivered by SSRT: Q2M are well documented high priorities for Europe and industry.  To quote a report published by just one example EU FP7 project, PROARTIS:

    "The market for Critical Real-Time Embedded Systems (CRTES), which among others includes the avionics and automotive sectors, is experiencing an unprecedented growth, and is expected to continue to steadily grow for the foreseeable future." ...  

    "The competition on functional value, measured in terms of application services delivered per unit of product faces CRTES industry with rising demands for greater performance, increased computing power, and stricter cost-containment.  The latter factor puts pressure on the reduction in the number of processing units and ECUs used in the system, to which industry responds by looking at more powerful processors with aggressive hardware acceleration features like caches and deep memory hierarchies...

    In this evolving scenario, it must be acknowledged that the industrial application of current WCET analysis techniques, which accounts for a significant proportion of total verification and validation time and cost of system production, yields far from perfect results.  IBM has for example found that 50% of the warranty costs in cars are related to electronics and their embedded software, and that 30% of those costs are related to timing flaws.  These instances of incorrect operation cost industry billions of Euros annually."
    [See article here]

    The CRTES market includes automotive, aerospace and defense, aviation, industrial control, robotics and the Internet of Things (CISCO: 50 billion devices expected by 2020).   SSRT: APRP  and  SRT: Q2M  are designed to service the CRTES market with a low-cost, easy to implement, easy to support, easy to exploit solution that adds new capabilities while reducing costs.

  • Better security:  Efficient control of timing and covert timing channels

    Modern high assurance real-time operating systems (RTOS) are capable of controlling the security risks that arise from covert timing channels within a single core system (and in multi-core systems if they prevent tasks of a different security class running concurrently on any other core).

    The SSRT family is designed from the ground up with the goal of eliminating covert timing channels across shared hardware resources such as network-on-chip interconnect and shared memory resources in mixed criticality, multi-core systems.  The SSRT family permits tasks of different security levels to run concurrently within the same chip over multiple cores. 

    • SSRT: Q2M offers basic covert timing channel resistance when required at run-time, permitting one to four tasks to be isolated from all other bus-masters. 
    • In contrast, SSRT: APRP and SSRT: Revolution offer comprehensive covert timing channel resistance between each and every bus-master (cores and perpiherals) when required at run time.  

    The SSRT Family is also designed to support constant time execution of functions within each "single core equivalent" environment. 

Comparison of SSRT family member capabilities 


SSRT: APRP   SSRT: Q2M     SSRT: Revolution




Commercially relevant high performance when implemented in FPGA yes boutique boutique
Supports mixing of time analyzable cores and fast-per-task cores in one chip (add Q2M) yes yes
Maximum number of processor cores supported (limited by cluster on chip or by chip) ≤16 per cluster ≤16 per chip ≤1000 per cluster
Maximum number of concurrently active real-time tasks ≤ 16 per cluster ≤ 4 total ≤ 4000 total
Maximum number of peripherals supported (limited by cluster on chip or by chip) ≤64 per cluster no fixed limit (add APRP)
Supports full coherency of memory between all cores yes yes yes




Suitable for use with today's mainstream CPU instruction sets yes yes yes
Hardware IP (CPU, Cache, NoC, Memory, Peripheral) vendor neutral yes yes yes
Real-time / general-purpose operating system vendor neutral yes yes yes
Supports event-driven and timing-driven scheduling yes yes yes




Can be implemented without any changes to third party soft macros yes yes no
Must be ported to different instruction set no no no
Must be ported to different network on chip protocols yes yes n/a
Must be ported to different memory controllers no yes no




Difficulty level to port Real-time Operating Systems (RTOS) low low medium
Difficulty level to port real-time programming languages very low very low very low
Difficulty level to port End User Applications low low low




Suitable for running broad classes of real-time applications yes yes yes
Will enable hard real-time tasks to run safely on multi-cores yes yes yes
Will enable mixed criticality app’s to run safely and securely in multi-cores yes yes yes
Number of cores optimised for running general purpose applications ≤ 1 core per cluster ≤ 12 cores ≤ 4 fast cores
Targeted as low-cost upgrade path for existing single-core designs yes yes n/a




Supports mixed criticality shared access of SDRAM channel (add Q2M) yes optional
Maximum number of real-time Single Core Equivalent (SCE) contexts ≤ 16 per cluster ≤ 4 ≤ 4000
Real-time and general purpose tasks can run concurrently with all cores active yes yes yes
Maximum number of Single Bus Master Peripheral Equivalent (SPE) contexts ≤ 64 per cluster (add APRP) (add APRP)
Can deterministically access peripherals from within SCE contexts yes yes yes
Can deterministically access ALL peripherals from within each SCE context yes (add APRP) (add APRP)
Aggregate peripheral memory bandwidth (gigabit/s) ≥ 500 gigabit/s (add APRP) (add APRP)
Supports dynamically optimising system performance based on active tasks yes yes no




Suitable for static and dynamic (measurement based) WCET analysis yes yes yes
Multi-core Worst Case Execution Time quality is equivalent to single-core yes yes yes
Difficulty level to control software timing interference with all cores active low low low
Difficulty level to control peripheral timing interference with all cores active low low with APRP low with APRP




Supports near or actual deterministic timing operation near near actual
Supports clock cycle deterministic operation even under preemption no no yes
Supports resource locking with zero unwanted timing interference limited yes yes
Supports clock-cycle deterministic message passing yes yes always
Can achieve more efficient use of power yes yes yes



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Synaptic Laboratories Limited: Technologies For A Safe and Secure High Performance Computing and Communications Ecosystem.