SLL Multi Bus Memory Controller (MBMC) IP v3

for Winbond HyperBus™ 1.0, HyperBus 2.0, and OctalNAND

SLL’s new Multiple Bus Memory Controller (MBMC) IP v3:
  • Multiple protocol support, in SLL’s unified MBMC IP
    • Supports PSRAM (low power replacement for SDR, LPDDRx, DDRx, DDRxL SDRAM)
    • Support for NAND Flash coming soon (for low-cost per bit and largest storage capacities)
  • Supports Winbond’s low-pin count memory device HyperRAM variants:
    • Winbond® x8 HyperRAM™ 1.0
    • Winbond® x8 HyperRAM™ 2.0  
  • Memory device support under active development includes:
    • Winbond® OctalNAND for use with Linux
    • (W35N01JW, W35N02JW, W35N04JW)
  • SLL is performing extensive testing of many device variants in hardware to reduce customer risk
  • Supports memory channels running at up to 200 MHz DDR on many FPGA device families
  • Supports 2 or more instantiations of memory controller IP in one FPGA design
  • You can find a wide range of HyperBus™ and CRUVI Boards from our board partners below.
  • Supports Intel FPGA, Microchip FPGA and Xilinx FPGA (see below)
  • Is based on SLL’s proven HyperBus Memory Controller (HBMC) IP for HyperBus™ 1.0 devices
    • Bundled with the Intel® Cyclone® 10 LP Evaluation Kit sold by Intel here, and by all Intel distributors (Arrow, Digi-Key, Magnica, etc)
    • Customers include industrial consortia, high profile government scientific organisations, universities, Fortune Global 500’s down to SME’s around the globe, from USA to China. 
  • Applications Include commercial and industrial projects and products:
    • Sensors, video, visioning, industrial automation, medical, transport, photonics, …
  • Transition easily from HyperBus™ 1.0 to HyperBus™ 2.0:
    • SLL HyperBus™ 1.0 customers are already successfully employing 200 MHz HyperBus™ 2.0 devices using SLL’s IP  
  • To request a free trial, please email:  info@synaptic-labs.com
SLL MBMC supports 8-, 16- and 32-bit datapaths
to address a broad range of use-cases, including:
16-bit tightly coupled PSRAM memory channel:
  • MBMC 2.0 supports accessing two PSRAM devices in parallel to double the wire speed memory bandwidth
  • Ideal for video frame applications
Up to four independent x8 memory channels in one FPGA design:
  • Each soft processor core can have its own private memory subsystem for optimal performance and determinism
Interleaved memory access across multiple PSRAM memory channels:
  • Create a 16-bit channel using 2 interleaved x8 channels  (preliminary support available for AXI4)
  • Create a 32-bit channel using 4 interleaved x8 channels  (preliminary support available for AXI4)
  • Create a 32-bit channel using 2 interleaved x16 channels (under development)
Developer resources
  • Please validate your pin-out and board design with Synaptic Labs, your FPGA vendor, and your memory vendors before manufacturing your first prototype.
    • Please contact Synaptic Laboratories at info@synaptic-labs.com to validate the memory channel pin-outs for your specific FPGA device before manufacture.
SLL Partners
MBMC has been ported to several Intel FPGA device families

SLL’s MBMC is many times smaller than any DDRx SDRAM controller IP available for Intel FPGA.  Furthermore, x8 HyperRAM requires approximately 3x less pins than x8 DDRx, making it ideal in resource constrained designs.

Memory channel clock speeds:
  • Supports full 200 MHz @ 1.8v and 133 MHz @ 3.0v clock speeds on:
    • All Cyclone 10 GX, Arria 10, Arria 10 SoC. 
  • Supports up to 200 MHz @  1.8V on some Cyclone 10 LP
    • Targeting 180-to-200 MHz @  1.8V on all Cyclone 10 LP devices
  • Targeting 180-to-200 MHz @  1.8V on all MAX 10 devices
  • Supports around 140 to 150 MHz @ 1.8V on Cyclone V and Cyclone V SoC
Additional features:
  • Automatically configures HyperRAM devices at power on
  • Memory devices immediately available for read/write access without a customer boot loader.
  • Internal clock-crossing logic to reduce circuit area of customer’s design.
  •  
MBMC IP has been ported to Microsemi PolarFire FPGA

SLL is Microchip’s chosen vendor to support up to 200 MHz HyperBus devices on Microsemi PolarFire devices

MBMC IP is complementary to PolarFire’s DDRx solutions:
  • Up to 200 MHz memory channel at 1.8V
  • Up to 133 MHz memory channel at 3.0V
  • Supports AXI4 interface
  • Supports GUI configuration in Libero
  • Up to 19x less FPGA Logic Elements (LE) than x16 DDR3L controller
  • Up to 5x less FPGA I/O pins than x16 DDR3L
  • Up to 4x less FPGA I/O pins than x8 DDR3L
  • RISC-V software performance on 8-bit HyperRAM @ 200 MHz is highly competitive with 16-bit DDR3 @ 333 MHz
  • Automatically configures memory devices at power on
  • Immediately available for read/write access without a customer boot loader
  • Internal clock-crossing logic to reduce circuit area of customer’s design.

Contact us at info@synaptic-labs.com to enrol for the Beta under our Early Access Program.

MBMC IP has been ported to Xilinx Series-7 devices
  • SLL has physically tested MBMC IP on several Artix-7, Spartan-7 and And Zynq-7000 boards from Trenz Electronic GmbH.
  • Supports AXI4 interface
  • Supports GUI configuration in Vivado
  • Automatically configures memory devices at power on
  • Memory devices immediately available for read/write access without a customer boot loader.
  • Synaptic Labs is working on upgrading our IP to support up to 200 MHz on Series-7 devices.
SLL can port our MBMC IP to support Efinix Trion FPGA

Please contact SLL on info@synaptic-labs.com to register your interest with regard to MBMC IP support on Efinix FPGA devices.

SLL can port our MBMC IP to Lattice FPGA

Including:

  • Lattice MachXO2 FPGA
  • and other Lattice FPGA devices.

 

Please contact SLL on info@synaptic-labs.com to register your interest with regard to MBMC IP support on one or more Lattice FPGA devices.

Please contact SLL on info@synaptic-labs.com to learn about the use of our IP in standard cell ASIC designs.

Status of Winbond HyperBus 2.0 compatible memory device testing and qualification performed by SLL (as of December 2019):

  • Winbond –  HyperRAM 2.0
    • Validated in the Simulator
      • W956D8MBYA5I (64 Mbit, 1.8V)
      • W956D8MBYA6I (64 Mbit, 1.8V)
      • W956A8MBYA5I (64 Mbit, 3.0V)
      • W956A8MBYA5I (64 Mbit, 3.0V)
    • Support available on customer request:
      • W955D8MBYA6I (32 Mbit, 1.8V)
      • W957D8MFYA5I (128 Mbit, 1.8V)
      • W957A8MFYA5I (128 Mbit, 3.0V)
      • W957A8MFYA6I (128 Mbit, 3.0V)
Status of board testing and qualification performed by SLL (as of October 2019):
Status of board testing and qualification performed by SLL (as of October 2019):
  • Trenz Electronic GmbH
    • CRUVI enabled MAX 10 baseboard – Pending
    • CRUVI enabled C10 LP baseboard – Pending