Bidirectional Channel over xSPI – Target IP

SLL Partners and Supported FPGA and Memory Vendors

SLL’s “Target xSPI Channel Peripheral” is used to provision bidirectional communications over JEDEC xSPI Profile 2.0. This permits high-bandwidth low-latency communications between {ASIC MCU <-> FPGA}, and {FPGA <-> FPGA} over xSPI protocol.

SLL’s xSPI Target xSPI Channel Peripheral:

  • supports up to 200 MHz DDR clock speed
  • relies on a strict subset of the PSRAM commands of JEDEC xSPI – Profile 2.0.
    a) Supports xSPI burst read / write operations for high effective memory bandwidth.
    b) Supports “xSPI Profile 2.0 Standard Command Modifier Format” and “xSPI Profile 2.0 Extended Command Modifier Format”.
  • multiplexes two communications channels over the xSPI channel to enable bidirectional communications.
  • each communications channel implements a bin-based flow control algorithm for high performance.
  • supports a range of different FPGA and ASIC targets:
    a) Intel Cyclone 10 LP
    b) Xilinx Zynq Ultrascale+
    c) standard cell ASIC
    d) Send an email to with requests for support on other targets.
  • is compatible with a broad range of memory controllers, including:
    a) SLL’s xSPI Multiple Bus Memory Controller (xSPI-MBMC) IP v3.x operating in:

i) HyperRAM(TM) 1.0 mode
ii) HyperRAM(TM) 2.0 mode
iii) JEDEC xSPI Profile 2.0 PSRAM mode

b) Send an email to with questions about compatibility with your preferred microcontroller unit (MCU).

Send an email to to learn more about this solution.

Contact SLL for information on many development board options for all these memory vendors xSPI memory devices: