Laboratories

SLL Multiple Bus Memory Controller (MBMC) IP

for HyperBus™ 1.0 and 2.0, OctaBus™, Xccela® Bus,

JEDEC® xSPI (JESD251) Profile 1.0 and Profile 2.0, …

8-, 16-, 32-Bit Datapath

Intel FPGA Configuration

SLL Partners

Microchip FPGA

Lattice FPGA

Standard Cell ASIC

AP Memory Xccela PSRAM

AP Memory OctaRAM

Cypress HyperFlash 1.0

Cypress HyperRAM 1.0

Cypress HyperMCP 1.0

Cypress SemperFlash (HyperFlash 2.0)

Cypress HyperRAM 2.0

ISSI HyperFlash 1.0

ISSI HyperRAM 1.0

ISSI Octal Flash

ISSI Octal RAM

Winbond HyperRAM 1.0 and 2.0

Winbond OctalNAND

Aries Embedded

Critical Link

Trenz Electronic

SLL Multiple Bus Memory Controller (MBMC) IP

for HyperBus™ 1.0 and 2.0, OctaBus™, Xccela® Bus,

JEDEC® xSPI (JESD251) Profile 1.0 and Profile 2.0, …

SLL Multiple Bus Memory Controller (MBMC) IP

for HyperBus™ 1.0 and 2.0, OctaBus™, Xccela® Bus,

JEDEC® xSPI (JESD251) Profile 1.0 and Profile 2.0, …

Get to market faster, with lower power consumption, lower pin count, lower cost, and far lower project risk by using SLL’s memory controller in your project/s.

SLL MBMC supports 8-, 16- and 32-bit datapaths to address a broad range of use-cases, including:

16-bit tightly coupled PSRAM memory channel:

Up to four independent x8 memory channels in one FPGA design:

Interleaved memory access across multiple PSRAM memory channels:

SLL is collaborating with Intel, Infineon, on Active Serial configuration of Intel FPGA devices using “Semper NOR Flash with HyperBus Interface”

Developer resources

Please validate your pin-out and board design with Synaptic Labs, your FPGA vendor, and your memory vendors before manufacturing your first prototype.

Please contact AP Memory at enquiry@apmemory.com for:

Please contact Cypress for:

MBMC has been ported to several Intel FPGA device families

Memory channel clock speeds:

Additional features:

MBMC IP has been ported to Microsemi PolarFire FPGA

MBMC IP is complementary to PolarFire’s DDRx solutions:

MBMC IP has been ported to Xilinx Series-7 devices

SLL can port our MBMC IP to support Efinix Trion FPGA

SLL can port our MBMC IP to Lattice FPGA

Status of AP Memory Xccela PSRAM device testing and qualification performed by SLL (as of January 2020):

Status of AP Memory OctaRAM device testing and qualification performed by SLL (as of January 2020):

Status of Cypress HyperFlash device testing and qualification performed by SLL (as of January 2020):

Status of Cypress HyperRAM 1.0 device testing and qualification performed by SLL (as of January 2020):

Status of Cypress HyperMCP 1.0 device testing and qualification performed by SLL (as of January 2020):

Status of Cypress “Semper NOR Flash with HyperBus interface” (HyperFlash 2.0) memory device testing and qualification performed by SLL (as of January 2020):

Status of Cypress HyperRAM 2.0 memory device testing and qualification performed by SLL (as of February 2020):

Status of ISSI HyperFlash 1.0 device testing and qualification performed by SLL (as of December 2019):

Status of ISSI HyperRAM 1.0 memory device testing and qualification performed by SLL (as of December 2019):

Status of ISSI Octal Flash device testing and qualification performed by SLL (as of December 2019):

Status of board testing and qualification performed by SLL (as of October 2019):

Status of board testing and qualification performed by SLL (as of October 2019):

Status of board testing and qualification performed by SLL (as of October 2019):

Status of board testing and qualification performed by SLL (as of October 2019):

Status of board testing and qualification performed by SLL (as of October 2019):

Status of board testing and qualification performed by SLL (as of October 2019):

Status of board testing and qualification performed by SLL (as of October 2019):

SLL MBMC supports 8-, 16- and 32-bit datapaths
to address a broad range of use-cases, including:

SLL is collaborating with Intel, Infineon, on
Active Serial configuration of Intel FPGA devices
using “Semper NOR Flash with HyperBus Interface”