SLL Multiple Bus Memory Controller (MBMC) IP

Get to market faster, with lower power consumption, lower pin count, lower cost, and far lower project risk by using SLL’s memory controller in your project/s.

To request a free trial, please email:  info@synaptic-labs.com

• Multiple protocol, multiple vendor support, in SLL’s unified memory controller IP
  
  • Reduce supply risk with multiple vendor sourcing options, from several countries
  • Supports any combination of 2 memory devices (with same data path width) on shared pins
  • Ensure both short term and long term availability of memory devices for your project
  • Supports PSRAM (low power replacement for SDR, LPDDRx, DDRx, DDRxL SDRAM)
  • Supports NOR Flash (for fast random read access and long term data retention)
  • Support for NAND Flash coming soon (for low-cost per bit and largest storage capacities)
• Supports well over 50 different low-pin count memory device variants:
  
  • AP Memory® x8 Xccela™ PSRAM
  • AP Memory® x8 OctaRAM™
  • AP Memory® x4 PSRAM (APS1604M-DQ)
  • Cypress®/Infineon® x8 HyperRAM™ 1.0 
  • Cypress®/Infineon® x8 HyperFlash™ 1.0 
  • Cypress®/Infineon® x8 HyperMCP 1.0 
    (HyperRAM™ 1.0 and HyperFlash™ 1.0 in a multi-chip package)
  • Infineon® x8 HyperRAM™ 2.0 with HyperBus™ Interface
  • Infineon® x8 Semper™ Flash with HyperBus™ Interface (HyperFlash™ 2.0)
  • Integrated Silicon Solution Inc.® (ISSI) x8 HyperRAM™ 1.0
  • ISSI® x8 HyperFlash™ 1.0
  • ISSI® x8 HyperMCP 1.0
    
  • Jeju Semiconductor Corp® (JSC) x8 OctaRAM™
  • Macronix® x8 OctaBus™ / OctaFlash™ (NOR Flash)
  • Micron® x8 Xccela™ Flash (NOR Flash)
  • Winbond® x8 HyperRAM™ 1.0
  • Winbond® x8 HyperRAM™ 2.0  
• Memory device support under active development includes:
  
  • AP Memory®  x16 Xccela™ PSRAM
  • Everspin® x8 xSPI Industrial STT-MRAM Persistent Memory (EM064LX)
    • in xSPI Profile 1.0 mode (e.g. NOR Flash emulation mode)
    • in persistent memory mode  (e.g. non-volatile PSRAM mode)
  • Gigadevice® x8 NOR Flash (GD25X, GD25LX)
  • Infineon® x8 HyperRAM™ 2.0 with Octal Interface 
  • Infineon® x8 Semper™ Flash with Octal Interface 
  • ISSI® x8 HyperRAM™ with inbuilt ECC 
  • ISSI® x8 OctalRAM™ 
  • ISSI® x8 OctalRAM™ with inbuilt ECC
  • Winbond® OctalNAND for use with Linux
    (W35N01JW, W35N02JW, W35N04JW)
• SLL can also add support the following memory devices:
  
  • JEDEC® xSPI (JESD251) Profile 1.0
    
    • NOR-MEM x8 NOR Flash
  • Other devices available on request. 
• SLL has performed extensive testing of many device variants in hardware to reduce customer risk
• Supports memory channels running at up to 200 MHz DDR on many FPGA device families
• Supports 2 or more instantiations of memory controller IP in one FPGA design
• You can find a wide range of HyperBus™ and CRUVI Boards from our board partners below.
• Supports Intel FPGA, Microchip FPGA and Xilinx FPGA (see below)
• Is based on SLL’s proven HyperBus Memory Controller (HBMC) IP for HyperBus™ 1.0 devices
  • Bundled with the Intel® Cyclone® 10 LP Evaluation Kit sold by Intel here, and by all Intel distributors (Arrow, Digi-Key, Macnica, etc)
  • Customers include industrial consortia, high profile government scientific organisations, universities, Fortune Global 500’s down to SME’s around the globe, from USA to China. 

• • Applications Include commercial and industrial projects and products:
    
    • Sensors, video, visioning, industrial automation, medical, transport, photonics, …
  • Transition easily from HyperBus™ 1.0 to HyperBus™ 2.0:
    
    • SLL HyperBus™ 1.0 customers are already successfully employing 200 MHz HyperBus™ 2.0 devices using SLL’

SLL MBMC supports 8-, 16- and 32-bit datapaths
to address a broad range of use-cases, including:

16-bit tightly coupled PSRAM memory channel:

• MBMC 2.0 supports accessing two PSRAM devices in parallel to double the wire speed memory bandwidth
• Ideal for video frame applications

Up to four independent x8 memory channels in one FPGA design:

• Each soft processor core can have its own private memory subsystem for optimal performance and determinism

Interleaved memory access across multiple PSRAM memory channels:

• Create a 16-bit channel using 2 interleaved x8 channels  (preliminary support available for AXI4)
• Create a 32-bit channel using 4 interleaved x8 channels  (preliminary support available for AXI4)
• Create a 32-bit channel using 2 interleaved x16 channels (under development)

SLL is collaborating with Intel, Infineon, on
Active Serial configuration of Intel FPGA devices
using “Semper NOR Flash with HyperBus Interface”

This will enable the Semper Flash device used for (1S-1S-1S) configuration of the FPGA to then be accessed with high bandwidth (8D-8D-8D) from within the FPGA fabric.  

The performance of  “Semper Flash with HyperBus Interface”  devices is very similar to PSRAM at a given clock speed, permitting execution of code in place from Semper Flash.

Contact us on info@synaptic-labs.com to explore the benefits of replacing very slow EPCQ/QSPI configuration flash with fast Semper Flash with re-use of the fast Semper Flash across FPGA designs. 

Developer resources

• Please validate your pin-out and board design with Synaptic Labs, your FPGA vendor, and your memory vendors before manufacturing your first prototype.

• • Please contact Synaptic Laboratories at info@synaptic-labs.com to validate the memory channel pin-outs for your specific FPGA device before manufacture.

• Please contact AP Memory at  enquiry@apmemory.com  for:

  • Xccela PSRAM data sheets
  • OctaRAM data sheets
  • AP Memory, “OPI 24B/90B board design guide”, 5 March 2019.

• Please contact Cypress for:

  • Cypress AN211622 – HyperFlash and HyperRAM Layout Guide
    
    • AN211622 discusses the layout considerations when placing a Cypress HyperFlash or HyperRAM device on a PCB.
  • Datasheets and guidance for 1st generation HyperRAM and HyperFlash
  • Datasheets and guidance for “Semper Flash with HyperBus Interface” (2nd generation HyperFlash)