Multiple Bus Memory Controller (MBMC) v3.2.x

for HyperFlash™ 1.0, HyperRAM™ 1.0, OctaRAM™, Xccela® PSRAM

Main product page​

SLL Partners and Supported FPGA and Memory Vendors for MBMC v3.2.x

MBMC v3.2.x product overview

SLL’s unified Multiple Bus Memory Controller (MBMC) v3.2.x IP supports a wide range of x8 DDR NOR Flash and x8 DDR PSRAM memories ( HyperFlash 1.0, HyperRAM 1.0, OctaRAM and Xccela PSRAM) that are available now from several memory vendors.

The low pin count (11 to 12 user I/O pins) memories offer good performance with lower hardware and power costs.  Memory device variants offer up to 128 Mbit PSRAM, up to 1 Gigabit NOR Flash, up to 200 MHz DDR clock speeds, with a x8 wide data path, and {6 mm x 8 mm} and {8 mm x 8 mm} BGA24 package options.  

SLL’s official partners include many of the leading global memory vendors.  SLL works closely with our partners to ensure SLL’s memory controllers are physically qualified with their memory device variants, significantly reducing your project’s risks.

SLL’s small MBMC IP v3.2.x enables you to easily evaluate, select and adopt the benefits of the latest x8 DDR memories in your projects and products.

SLL provides world class pre-sales and post-sales technical support for all the major memory vendors and FPGA vendors, helping you navigate the rapidly evolving market, on the platform of your choice.

Get to market faster, with lower power consumption, lower pin count, lower cost, and far lower project risk by using SLL’s memory controller in your project/s.

Note:  If you need a broader range of memory device support, please see SLL’s xSPI MBMC IP v.3.3.x product page here.

MBMC v3.2.x support for FPGA targets

This memory controller IP has been ported to, and physically tested on, a broad range of FPGA device variants, including:

  • Most modern Intel FPGA device families, including:
    • Intel MAX 10
    • Cyclone IV
    • Cyclone 10 LP
    • Cyclone 10 GX
    • Cyclone V
    • Cyclone V SoC
    • Arria 10
    • Arria 10 SoC
    • Stratix 10
  • Most modern Xilinx FPGA device families, including:
    • Artix-7
    • Kintex-7
    • Virtex-7
    • Zynq 7000
    • Kintex Ultrascale+
    • Zynq Ultrascale+

For even broader FPGA device family support, and for ASIC standard cell support, please visit our xSPI MBMC IP v3.3.x product page

MBMC v3.2.x Trial

To request a Trial for selected FPGA device families, please visit here.

MBMC v3.2.x Capabilities

  • Includes tight integration with Intel’s Platform Designer and Xilinx’s Vivado graphical system integration tools  
  • Features high quality local interconnect, with support for the following interconnect protocols:
    • ARM AMBA AXI4 protocol
    • ARM AMBA APB3 protocol
    • Intel Avalon-MM protocol
    • other interconnect protocols available on request…
  • Includes internal clock-crossing circuitry between the local bus interconnect and the external memory channel to reduce circuit area and improve the performance of the customer’s design
  • Excellent memory access performance for both latency sensitive and bandwidth intensive applications:
    • The round trip time for read memory transfer requests through the memory controller has been optimized for latency sensitive applications, such as processor cores.
    • The memory controller supports long burst memory transfer requests over the memory channel to sustain high effective memory bandwidth (>90% efficiency of memory channel)
    • Note:  SLL offers a range of cache technologies to significantly increase the performance of  processor cores that do not have internal instruction and/or data caches when accessing external memories.
  • Features low circuit area and low SRAM usages, making SLL’s memory controller viable for use in resource constrained designs. 
  • Includes optional support for automatic configuration of memory devices at power on:
    • FPGA customers typically use the automatic configuration option
    • This dramatically simplifies integration of SLL’s memory controller in customer designs, enabling all firmware to be executed in place from x8 NOR Flash.  
  • Include support for manual configuration of the memory controller and any attached memory devices
  • Supports x8 data path width in a single instantiation of SLL’s memory controller IP
  • Supports 2 or more instantiations of the memory controller IP in one project
    • Preliminary support for splitting AXI4 requests across 2 instances of the memory controller in parallel to double memory bandwidth is now available

MBMC v3.2.x markets, applications and use cases

Customers include industrial consortia, high profile government scientific organisations, universities, Fortune Global 500’s down to SME’s around the globe, from USA to China.   Applications include commercial and industrial projects and products, such as:  Sensors, video, industrial automation, medical, transport, photonics, …   Use cases include:  eXecution in Place (XiP) of software, long burst DMA access, video frame buffering, packet buffering, …

MBMC v3.2.x support for memory devices

SLL’s MBMC v3.2.x supports, and is physically qualified with, a broad range of HyperFlash, HyperRAM, OctaRAM and Xccela PSRAM device variants.

  • Supports HyperRAM 1.0, HyperRAM 2.0 with HyperBus Interface, OctaRAM, Octal RAM and Xccela PSRAM (low power replacement for SDR, LPSDR, DDR and CellularRAM)
  • Supports HyperFlash 1.0, and SemperFlash with HyperBus Interface (HyperFlash 2.0) for fast random read access and long term data retention
  • Supports memory devices with x8 data paths
  • Supports mixing-and-matching memory types {PSRAM, PSRAM}, {NOR Flash, PSRAM}, {NOR Flash, NOR Flash} with the same data path width on shared pins
  • Supports use of different bus protocols, such as {SemperFlash with HyperBus interface, OctaRAM}, {HyperFlash 1.0, Xccela PSRAM} on shared pins
  • Use of SemperFlash with HyperBus Interface for power on configuration of Intel Cyclone 10 LP in 1S-1S-1s mode, and high speed re-use of that memory device in 8D-8D-8D mode to reduce bill of materials and increase system performance

SLL’s MBMC v3.2.x supports a broad range of memory vendors:

  • Ensures both short term and long term availability of memory devices for your project
  • The ability to source memory devices, from these major memory vendors, reduces your supply chain risk

In line with recommendations from major memory vendors, SLL strongly recommends that customers ensure that the most up-to-date product order codes and the latest die revisions are employed during each manufacturing run of your product to ensure lowest power and best system performance Therefore, SLL does not support legacy memory devices in new product designs.

MBMC v3.2.x currently supports, or will very soon support:

MBMC v3.2.x enables easy transition from HyperBus™ 1.0 to HyperBus™ 2.0.
SLL’s HyperBus™ 1.0 customers are already successfully employing 200 MHz HyperBus™ 2.0 devices at up to 200 MHz DDR in FPGA.

For even broader memory device support, including JEDEC xSPI Profile 1.0 memory devices, please visit SLL’s xSPI MBMC v3.3.x product page.

MBMC v3.2.x support for Commercial-off-the-shelf (COTS) boards

SLL has the broadest range of board partners in this memory controller market.  SLL has also tested our memory controller on the broadest range of COTS and proprietary boards in the market.

SLL leverages our close relationships to deliver known-working reference designs with trial copies of MBMC v3.2.x (that do not expire) to:  (a) reduce your project risk; and (b) get you to market faster.  SLL’s board partners include:

SLL has also run our memory controller IP on boards from other board vendors such as:

MBMC v3.2.x developer resources

  • To reduce design risks, please validate your pin-mapping and PCB layout for your selected memory devices with Synaptic Laboratories at before manufacturing your first prototype.
  • Please email for SLL’s guidance with regard to supporting specific FPGA device families.
  • SLL is the domain expert for xSPI memories. We have supported Fortune Global 500’s down to SME’s around the globe to project success in many applications using xSPI memories. You are invited to contact SLL if you would like any input on your project design and objectives using xSPI memories.

Contact SLL for information on many development board options for all these memory vendors xSPI memory devices: