xSPI Multiple Bus Memory Controller (xSPI-MBMC)

for HyperBus™ 1.0 and 2.0, OctaBus™, Xccela® Bus,

JEDEC® xSPI (JESD251) Profile 1.0 and Profile 2.0, …

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SLL Partners and Supported FPGA and Memory Vendors

xSPI MBMC v3 overview

SLL’s unified xSPI Multiple Bus Memory Controller IP supports the widest range of JEDEC xSPI and xSPI-like NOR Flash and PSRAM memories (JEDEC xSPI Profile 1.0 and 2.0, HyperBus 1.0 and 2.0, OctaBus and Xccela Bus) that are available now from many memory vendors.

JEDEC xSPI and xSPI-like memories offer good performance with lower hardware and power costs.  Memory device variants offer up to 512 Mbit PSRAM, up to 2 Gigabit NOR Flash, up to 200 MHz DDR clock speeds, with x4, x8 and x16 data path widths, and a wide range of package options including 4mm x 4mm BGA49 and tiny WLCSP footprints.  Some PRSAM devices are now also available with internal ECC.

SLL’s official partners include many of the leading global memory vendors.  SLL works closely with our partners to ensure SLL’s memory controllers are physically qualified with their memory device variants, significantly reducing your project’s risks.

SLL’s small MBMC IP enables you to easily evaluate, select and adopt the benefits of the latest xSPI-style memories in your projects and products.

SLL provides world class pre-sales and post-sales technical support for all the major memory vendors and FPGA vendors, helping you navigate the rapidly evolving market, on the platform of your choice.

Get to market faster, with lower power consumption, lower pin count, lower cost, and far lower project risk by using SLL’s memory controller in your project/s.

xSPI MBMC v3 Free Trials

To request a free trial for selected FPGA device families, please email:  
        free-trials@synaptic-labs.com

xSPI MBMC v3 Capabilities

  • Tight integration with the EDA design tools
  • High quality local interconnect bus support
    • ARM AMBA AXI4/ABP3 support available 
    • Intel Avalon-MM support available 
    • other protocols available on request…
  • Optional internal clock-crossing logic to reduce circuit area of customer’s design
  • Excellent memory performance
    • Low read memory transfer request round trip times for latency sensitive bus-masters such as processor cores
    • Long burst optimised architecture for sustaining high effective memory bandwidth
    • Cache technologies available for processor cores that do not have internal instruction and/or data caches
  • Low logic element/gate and on-chip SRAM resources
  • Optional support for automatically configuration of memory devices at power on:
    • Memory devices immediately available for read/write access without a custom boot loader.
  • Optional support for manual configuration of memory controller and memory devices
    • Compatible with the ASIC port of xSPI MBMC IP
    • Use the FPGA port to prototype ASIC designs at high clock speeds
  • Supports 2 or more instantiations of memory controller IP in one project
    • Preliminary support for splitting AXI4 requests across 2 instances of xSPI MBMC IP in parallel to double effective memory bandwidth is available

xSPI MBMC v3 markets, applications and use cases

Customers include industrial consortia, high profile government scientific organisations, universities, Fortune Global 500’s down to SME’s around the globe, from USA to China.   Applications include commercial and industrial projects and products, such as:  Sensors, video, industrial automation, medical, transport, photonics, …   Use cases include:  eXecution in Place (XiP) of software, long burst DMA access, video frame buffering, packet buffering, …

xSPI MBMC v3 support for FPGA and ASIC targets

SLL’s xSPI MBMC IP has been ported to, and physically tested on, a broad range of FPGA device variants, including:
  • Most modern Intel FPGA from Cyclone IV through to Stratix 10
  • Most modern Xilinx FPGA device families, including all of the 7-Series and Ultrascale+
  • Microchip / Microsemi PolarFire FPGA
SLL’s xSPI MBMC IP is also currently being ported to standard cell ASIC.

xSPI MBMC v3 support for memory devices

SLL’s xSPI MBMC IP supports, and is physically qualified with, the broadest range of JEDEC xSPI Profile 1.0 and 2.0 and xSPI-like memory device variants in the market.
  • Supports PSRAM (low power replacement for SDR, LPDDRx, DDRx, DDRxL SDRAM)
  • Supports NOR Flash (for fast random read access and long term data retention)
  • Support for NAND Flash coming soon (for low-cost per bit and largest storage capacities)
  • Supports memory devices with x4, x8 and x16 data paths
  • Supports any combination of 2 memory devices (with same data path width) on shared pins
  • Use of selected x8 NOR Flash devices for power on configuration of Intel Cyclone 10 LP in 1S-1S-1s mode, and high speed re-use of that memory device in 8D-8D-8D
SLL’s xSPI MBMC IP supports the broadest range of memory vendors:
  • Ensures both short term and long term availability of memory devices for your project
  • The ability to source memory devices, from all major memory vendors, reduces your supply chain risk
xSPI MBMC IP currently supports, or will very soon support: xSPI MBMC IP enables easy transition from HyperBus™ 1.0 to HyperBus™ 2.0. SLL’s HyperBus™ 1.0 customers are already successfully employing 200 MHz HyperBus™ 2.0 devices at up to 200 MHz DDR in FPGA.

xSPI MBMC v3 support for Commercial-off-the-shelf (COTS) boards

SLL has the broadest range of xSPI and xSPI-like board partners in this memory controller market.  SLL has also tested our memory controller on the broadest range of COTS and proprietary boards in the market. SLL leverages our close relationships to deliver known-working reference designs with free trial copies of xSPI MBMC IP (that do not expire) to:  (a) reduce your project risk; and (b) get you to market faster.  SLL’s board partners include: SLL has also run our IP on boards from other board vendors such as:

xSPI MBMC v3 developer resources

  • Resources for specific memory device variants
  • Resources for FPGA device families ( link )
  • Please validate your pin-out and board design with Synaptic Labs, your FPGA vendor, and your memory vendors before manufacturing your first prototype.
  • Please contact Synaptic Laboratories at info@synaptic-labs.com to validate the memory channel pin-outs for your specific FPGA device before prototype manufacture.

Contact SLL for information on many development board options for all these memory vendors xSPI memory devices: info@synaptic-labs.com