MBMC has been ported to several Intel FPGA device families
SLL’s MBMC is many times smaller than any DDRx SDRAM controller IP available for Intel FPGA. Furthermore, x8 HyperRAM requires approximately 3x less pins than x8 DDRx, making it ideal in resource constrained designs.
Memory channel clock speeds:
- Supports full 200 MHz @ 1.8v and 133 MHz @ 3.0v clock speeds on:
- All Cyclone 10 GX, Arria 10, Arria 10 SoC.
- Supports up to 200 MHz @ 1.8V on some Cyclone 10 LP
- Targeting 180-to-200 MHz @ 1.8V on all Cyclone 10 LP devices
- Targeting 180-to-200 MHz @ 1.8V on all MAX 10 devices
- Supports around 140 to 150 MHz @ 1.8V on Cyclone V and Cyclone V SoC
- Automatically configures HyperRAM devices at power on
- Memory devices immediately available for read/write access without a customer boot loader.
- Internal clock-crossing logic to reduce circuit area of customer’s design.