SLL's embedded software innovation has been recognised by our customers and partners. Major FPGA, memory, and development board makers now officially partner with SLL. This ensures SLL IP is validated on a wide range of physical devices. SLL customers are located in most geographical regions, and include Fortune Global 500's, government agencies, and SME's from USA and Canada to China.
xSPI MBMC IP v3.3.x estimated effective bandwidth for AP Memory Xccela PSRAM and OctaRAM devices
For all DDRx SDRAM, and PSRAM devices, the effective memory bandwidth is always less than the wire speed. The effective memory bandwidth of your application using PSRAM devices depends on:
- The data path width of the memory channel (x8, x16, ..)
- The memory channel clock speed (ideally the highest speed supported by the memory device and SLL’s memory controller IP for that FPGA device family)
- The initial access latency (ideally the lowest value permitted by the PSRAM device for a given clock speed)
- The burst length of memory transfer requests issued to SLL’s memory controller IP (ideally 64 bytes or higher to PSRAM)
- The number of concurrently outstanding memory transfer requests issued to SLL’s memory controller IP (ideally 2)
- With all types of PSRAM devices, the temperature grade of the memory device impacts the maximum burst length of PSRAM devices.
- The choice of x8 OctaRAM or x8 Xccela PSRAM protocol does not have a significant impact on performance.
Use SLL’s estimated effective bandwidth calculator below to find the optimal burst length(s) for your application’s use-case when using SLL’s memory controller below with a specific Xccela PSRAM or OctaRAM device variant.