xSPI Multiple Bus Memory Controller (xSPI-MBMC) v3.3.x

Product page​ for

IoT RAM (Xccela™), IoT RAM (OctaRAM™), IoT RAM (x4 QSPI)

SLL is AP Memory’s partner for memory controller and related technologies.

SLL Partners and Supported FPGA Vendors for AP Memory's memory devices

Overview of xSPI MBMC IP v3.3.x support for AP Memory's memory devices

SLL’s xSPI Multiple Bus Memory Controller IP supports AP Memory IoT RAM (Xccela), IoT RAM (OctaRAM) and QSPI DDR PSRAM.

AP Memory’s range of PSRAM memories offer good performance with lower hardware and power costs. 

AP Memory IoT RAM (Xccela) device variants offer up to 512 Mbit of storage capacity, up to 200 MHz DDR clock speeds (up to 250 MHz with KGD), with x8 and x16 data path widths, and a wide range of package options including 4mm x 4mm BGA49 and tiny WLCSP footprints.  

AP Memory IoT RAM (OctaRAM) device variants offer up to 512 Mbit of storage capacity, up to 200 MHz DDR clock speeds, with x8 data path widths, and a wide range of package options including 4mm x 4mm BGA49 and tiny WLCSP footprints.  

AP Memory offer a 16 Mbit and 128 Mbit QSPI DDR SPI device with read data strobe to enable up to 166 Mbytes/s wire speed for use in pin constrained customer designs.  

SLL is one of AP Memory’s official partners for memory controller IP.  SLL works closely with AP Memory to ensure SLL’s memory controller is physically qualified with many of AP Memory’s memory device variants, significantly reducing your project’s risks.

SLL’s small MBMC IP enables you to easily evaluate, select and adopt the benefits of AP Memory’s latest memories in your projects and products.

SLL provides world class pre-sales and post-sales technical support for AP Memory and all the major memory FPGA vendors, helping you navigate the rapidly evolving market, on the platform of your choice.

Get to market faster, with lower power consumption, lower pin count, lower cost, and far lower project risk by using SLL’s memory controller in your project/s with AP Memory’s memory devices.

xSPI MBMC v3.3.x support for FPGA and ASIC targets

This memory controller IP has been ported to, and physically tested on, a broad range of FPGA device variants, including:

  • Most modern Intel FPGA device families, including:
    • Intel MAX 10 – Up to 200 MHz DDR
    • Cyclone IV 
    • Cyclone 10 LP – Up to 200 MHz DDR
    • Cyclone 10 GX – Up to 250 MHz DDR
    • Cyclone V
    • Cyclone V SoC
    • Arria 10 – Up to 250 MHz DDR
    • Arria 10 SoC – Up to 250 MHz DDR
    • Stratix 10 – Up to 250 MHz DDR
  • Most modern Xilinx FPGA device families, including:
    • Artix-7
    • Kintex-7
    • Virtex-7
    • Zynq 7000
    • Kintex Ultrascale+
    • Zynq Ultrascale+
    • Virtex Ultrascale+ (ideal for supporting ASIC design prototyping in FPGA)
  • Microchip (Microsemi)
    • PolarFire FPGA – Up to 250 MHz DDR

Other FPGA device families may be available on request. Please contact SLL at info@synaptic-labs.com with details about the specific currently unsupported FPGA device family that you would like to use.

This memory controller IP is also currently being ported from FPGA to standard cell ASIC at up to 250 MHz DDR with x4/x8/x16 datapath support.

xSPI MBMC v3.3.x Free Trials

To request a free trial for selected FPGA device families, please visit here.

xSPI MBMC v3.3.x Capabilities

  • Includes tight integration with all the major FPGA vendor’s graphical system integration tools (Platform Designer, Vivado, …)  
  • Features high quality local interconnect, with support for the following interconnect protocols:
    • ARM AMBA AXI4 protocol
    • ARM AMBA APB3 protocol
    • Intel Avalon-MM protocol
    • other interconnect protocols available on request…
  • Includes internal clock-crossing circuitry between the local bus interconnect and the external memory channel to reduce circuit area and improve the performance of the customer’s design
  • Excellent memory access performance for both latency sensitive and bandwidth intensive applications:
    • The round trip time for read memory transfer requests through the memory controller has been optimized for latency sensitive applications, such as processor cores.
    • The memory controller supports long burst memory transfer requests over the memory channel to sustain high effective memory bandwidth (>90% efficiency of memory channel)
    • Note:  SLL offers a range of cache technologies to significantly increase the performance of  processor cores that do not have internal instruction and/or data caches when accessing external memories.
  • Features low circuit area and low SRAM usages, making SLL’s memory controller viable for use in resource constrained designs. 
  • Includes optional support for automatic configuration of memory devices at power on:
    • FPGA customers typically use the automatic configuration option
    • This dramatically simplifies integration of SLL’s memory controller in customer designs, enabling all firmware to be executed in place from x8 NOR Flash.  
  • Include support for manual configuration of the memory controller and any attached memory devices
    • ASIC customers typically use the manual configuration option
    • ASIC customers can prototype their designs in FPGA with manual configuration option enabled
  • Supports x4, x8 and x16 data path width in a single instantiation of SLL’s memory controller IP
  • Supports 2 or more instantiations of the memory controller IP in one project
    • Preliminary support for splitting AXI4 requests across 2 instances of the memory controller in parallel to double memory bandwidth is now available

xSPI MBMC v3.3.x markets, applications and use cases for PSRAM

Customers include industrial consortia, high profile government scientific organisations, universities, Fortune Global 500’s down to SME’s around the globe, from USA to China.   Applications include commercial and industrial projects and products, such as:  Sensors, video, industrial automation, medical, transport, photonics, …   Use cases include:  execution of software, long burst DMA access, video frame buffering, packet buffering, …

xSPI MBMC v3.3.x support for AP Memory's memory devices

SLL’s memory controller supports, and is physically qualified with, a broad range of AP Memory’s memory device variants:

  • AP Memory IoT RAM (Xccela)
  • AP Memory IoT RAM (OctaRAM)
  • AP Memory IoT RAM (x4 QSPI)

xSPI MBMC v3.3.x support for AP Memory Xccela PSRAM

Status of AP Memory IoT RAM (Xccela) device testing and qualification performed by SLL:

  • AP MemoryIoT RAM (Xccela):
    • Physically validated:
      • APS1604M-DQRABA (x4, 16 Mbit, 1.8V)
      • APS6408L‐OBx  (x4, 64 Mbit, 1.8V)
      • APS12808L-OBx (x8, 128 Mbit, 1.8V)
    • Physically validated on Trenz board:
      • APS1604M-DQRABA (x4, 16 Mbit, 1.8V)
      • APS12808L-OBM-BA (x8, 128 Mbit, 1.8V)
      • APS12808L-3OBM-BA (x8, 128 Mbit, 3V)
      • APS25608N-OBM-BD (x8, 256 Mbit, 1.8V)
      • APS256XXN-OBR-BG (x8, 256 Mbit, 1.8V)
      • APS256XXN-OBR-BG (x16, 256 Mbit, 1.8V)
      • APS51208N-OBR-BD (x8, 512 Mbit, 1.8V)
    • Validated in simulator:
      • APS6408L-3OBx (x8, 64 Mbit, 3V)
      • APS12808L-3OB (x8, 128 Mbit, 3V)
      • APS25608N-OBRx  (x8, 256 Mbit, 1.8V)
      • APS51208N-OBRx (x8, 512 Mbit, 1.8V)
    • Validation planned:
      • APS12804O-DQ-WA (x4, 128 Mbit, 1.8V)
      • APS128XXN-OBR-BG (x8, 128 Mbit, 1.8V)
      • APS128XXN-OBR-BG (x16, 128 Mbit, 1.8V)
      • APS512XXN-OBR-BG (x8, 512 Mbit, 1.8V)
      • APS512XXN-OBR-BG (x16, 512 Mbit, 1.8V)

xSPI MBMC v3.3.x support for AP Memory OctaRAM

Status of AP Memory IoT (OctaRAM) device testing and qualification performed by SLL:

  • AP Memory – IoT (OctaRAM):
    • Physically validated:
      • APM6408L-OC (64 Mbit, 1.8V)
      • APM6408L-3OC (64 Mbit, 3.0V)
    • Physically validated on Trenz board:
      • APS6408L-30C (64 Mbit, 3.0V)
    • Validation pending:
      • APS25608N‐OCx (256 Mbit, 1.8V)
      • APS51208N‐OCx (512 Mbit, 1.8V)

xSPI MBMC v3.3.x support for Commercial-off-the-shelf (COTS) boards

SLL has the broadest range of xSPI and xSPI-like board partners in this memory controller market.  SLL has also tested our memory controller on the broadest range of COTS and proprietary boards in the market.

SLL leverages our close relationships to deliver known-working reference designs with free trial copies of xSPI MBMC v3.3.x (that do not expire) to:  (a) reduce your project risk; and (b) get you to market faster.  SLL’s board partners include:

SLL has also run our memory controller IP on boards from other board vendors such as:

Notice to Hardware Developers using xSPI MBMC v3.3.x

  • Please validate your pin-mapping and PCB Layout for you selected memory devices with Synaptic Laboratories at info@synaptic-labs.com before manufacturing your first prototype to reduce risks.
  • Please email info@synaptic-labs.com for SLL’s guidance with regard to supporting specific FPGA device families.

AP Memory IoT RAM (Xccela) Resources

  • AP Memory
  • Standards
    • Micron Xccela Bus Standard for PSRAM
  • Application notes and other guidance
    • AP Memory, “OPI 24B/90B board design guide”, 5 March 2019.
      • Request guidance by email
  • Data sheets:
    • APS -OB  x8
      • APS6408L‐OB   (x8,   64 Mbit, 1.8V)
        • APS6408L-OB                   (bare die)
        • APS6408L-OBX                (bare die)
        • APS6408L-OB-BA            (6mmx8mm 24BGA)
        • APS6408L-OBX-BA         (6mmx8mm 24BGA)
      • APS6408L‐OBM  (x8,   64 Mbit, 1.8V)
        • APS6408L-OBM                (bare die)
        • APS6408L-OBMX             (bare die)
        • APS6408L-OBM-BA         (6mmx8mm 24BGA)
        • APS6408L-OBMX-BA      (6mmx8mm 24BGA)
      • APS12808L-OB   (x8, 128 Mbit, 1.8V)
        • APS12808L-OB-BA          (6mmx8mm 24BGA)
        • APS12808L-OBX-BA        (6mmx8mm 24BGA)
        • APS12808L‐OBR-WB      (WLCSP)
        • APS12808L‐OBRC            (WLCSP)
        • APS12808L‐OBXRC         (WLCSP)
      • APS12808L-OBM   (x8, 128 Mbit, 1.8V)
        • APS12808L-OBM-BA       (6mmx8mm 24BGA)
        • APS12808L-OBMX-BA     (6mmx8mm 24BGA)
      • APS25608N-OBRx  (x8, 256 Mbit, 1.8V)
        • APS25608N-OBR               (bare die)
        • APS25608N-OBRX            (bare die)
        • APS25608N-OBR-BD        (6mmx8mm 24BGA)
        • APS25608N-OBRX-BD     (6mmx8mm 24BGA)
      • APS51208N-OBRx  (x8, 512 Mbit, 1.8V)
        • APS51208N-OBR               (bare die)
        • APS51208N-OBRX            (bare die)
        • APS51208N-OBR-BD        (6mmx8mm 24BGA)
        • APS51208N-OBRX-BD      (6mmx8mm 24BGA)
    • APS -OB  x8, x16
      • APS256XXN  (x8, x16, 256 Mbit, 1.8V)
        • APS256XXN-OBR                (bare die)
        • APS256XXN-OBRX             (bare die)
        • APS256XXN-OBR-BG         (6mmx8mm 24BGA)
        • APS256XXN-OBRX-BG      (6mmx8mm 24BGA)
        • APS256XXN-OBR-BE         (4mmx4mm 49BGA)
        • APS256XXN-OBRX-BE       (4mmx4mm 49BGA)
        • APS256XXN-OBR-WA        (24 WLCSP)
        • APS256XXN-OBRX-WA     (24 WLCSP)
      • APS512XXN-OBRx -BA   (x8, x16, 512 Mbit, 1.8V)
        • APS512XXN-OBR                (bare die)
        • APS512XXN-OBRX             (bare die)
        • APS512XXN-OBR-BG          (6mmx8mm 24BGA)
        • APS512XXN-OBRX-BG       (6mmx8mm 24BGA)
        • APS512XXN-OBR-BE          (4mmx4mm 49BGA)
        • APS512XXN-OBRX-BE       (4mmx4mm 49BGA)
    • APS -3OB
      • APS6408L-3OBx  (x8,   64 Mbit,  3V)
        • APS6408L-3OBM-BA         (6mmx8mm 24BGA)
        • APS6408L-3OBMX-BA      (6mmx8mm 24BGA)
      • APS12808L-3OB  (x8, 128 Mbit, 3V)
        • APS12808L-3OBM-BA       (6mmx8mm 24BGA)
        • APS12808L-3OBMX-BA     (6mmx8mm 24BGA)

AP Memory IOT RAM (OctaRAM) Resources

  • AP Memory
  • Standards
    • Macronix Octabus Standard for OctaRAM
  • Application notes and other guidance
    • AP Memory, “OPI 24B/90B board design guide”, 5 March 2019.
      • Request guidance by email
  • Data sheets:
    • APS-OC
      • APS6408L-OC (64 Mbit, 1.8V)
        • APS6408L-OC                     (bare die)
        • APS6408L-OCX                   (bare die)
        • APS6408L-OC-BA               (6mmx8mm 24BGA)
        • APS6408L-OCX-BA            (6mmx8mm 24BGA)
      • APS25608N‐OCx (256 Mbit, 1.8V)
        • APS25608N-OCH               (bare die)
        • APS25608N-OCHX            (bare die)
        • APS25608N-OCH-BA        (6mmx8mm 24BGA)
        • APS25608N-OCH-BA        (6mmx8mm 24BGA)
      • APS51208N‐OCx (512 Mbit, 1.8V)
        • APS51208N-OCH               (bare die)
        • APS51208N-OCHX            (bare die)
        • APS51208N-OCH-BA        (6mmx8mm 24BGA)
        • APS51208N-OCH-BA        (6mmx8mm 24BGA)
    • APS-3OC
      • APS6408L-3OC (64 Mbit, 3.0V)
        • APS6408L-3OC-BA            (6mmx8mm 24BGA)
        • APS6408L-3OCX-BA         (6mmx8mm 24BGA)

AP Memory IoT RAM (x4 QSPI) Resources

Contact SLL for information on many development board options for all these memory vendors xSPI memory devices: info@synaptic-labs.com