SLL's embedded software innovation has been recognised by our customers and partners. Major FPGA, memory, and development board makers now officially partner with SLL. This ensures SLL IP is validated on a wide range of physical devices. SLL customers are located in most geographical regions, and include Fortune Global 500's, government agencies, and SME's from USA and Canada to China.
xSPI Multiple Bus Memory Controller (xSPI-MBMC) v3.3.x
SLL Partners and Supported FPGA Vendors for Everspin memory devices
Overview of xSPI MBMC IP v3.3.x support for Everspin EMxxLX memory devices
EVERSPIN PRESS RELEASE ( 3 May 2022 )
Announces New STT-MRAM EMxxLX xSPI Family of Products that are supported by SLL’s xSPI MBMC IP:
- Persistent memory with up to 400 Megabytes/s read and write transfer rate
- Supports extremely fast xSPI Profile 1.0 NOR Flash emulation mode
- Supports PSRAM emulation mode with non-volatile storage
Read the ‘game changing’ summary about STT-MRAM by JBLopen Inc’s Edward Haas.
SLL’s is Everspin’s official partner for memory controller IP. Everspin uses SLL’s xSPI MBMC IP.
SLL works closely with Everspin to ensure SLL’s memory controller is physically qualified with many Everspin memory device variants, significantly reducing your project’s risks.
SLL’s small xSPI MBMC IP enables you to easily evaluate, select and adopt the benefits of Everspin’s latest memories in your projects and products.
Everspin’s new xSPI product family is based on the EXpanded Serial Peripheral Interface, the latest JEDEC standard for non-volatile memory devices. It is based on Everspin’s unique industrial STT MRAM technology. The products offer high-performance, multiple I/O, SPI-compatibility and feature a high-speed, low pin count SPI compatible bus interface with a clock frequency of up to 200 MHz. These persistent memory MRAM devices operate on a single 1.8V power supply and deliver up to 400MBps for both reads and writes via eight I/O signals.
This ushers in a new era of universal memory application solutions, replacing products such as SRAM, BBSRAM, NVSRAM and NOR devices, targeting Industrial Automation, Process Control, Emulation, Automotive and Transportation, Gaming, and the broader industrial IoT markets.
SLL provides world class pre-sales and post-sales technical support for Everspin and all the major memory FPGA vendors, helping you navigate the rapidly evolving market, on the platform of your choice.
Get to market faster, with lower power consumption, lower pin count, lower cost, and far lower project risk by using SLL’s memory controller in your project/s with Everspin’s innovative memory devices.
xSPI MBMC v3.3.x support for Everspin EMxxLX memory devices
SLL’s memory controller supports, and is physically qualified with, EMxxLX memory device variants that support write data strobe:
- Supports EMxxLX in 8D-8D-8D with data strobe mode with x8 PSRAM like performance
- Supports EMxxLX in 4D-4D-4D with data strobe mode with x4 PSRAM like performance
xSPI MBMC IP v3.3.x estimated effective bandwidth for Everspin EMxxLX
For all DDRx SDRAM, PSRAM and STT-MRAM devices, the effective memory bandwidth is always less than the wire speed. The effective memory bandwidth of your application using STT-MRAM devices depends on:
- The data path width of the memory channel (x8, x16, ..)
- The memory channel clock speed (ideally the highest speed supported by the memory device and SLL’s memory controller IP for that FPGA device family)
- The initial access latency (ideally the lowest value permitted by the STT-MRAM device for a given clock speed)
- The burst length of memory transfer requests issued to SLL’s memory controller IP (ideally 64 bytes or higher to STT-MRAM)
- The number of concurrently outstanding memory transfer requests issued to SLL’s memory controller IP (ideally 2)
- In contrast to PSRAM devices, the temperature grade of the memory device does not impact the maximum burst length of STT-MRAM devices.
Use SLL’s estimated effective bandwidth calculator below to find the optimal burst length(s) for your application’s use-case when using SLL’s memory controller below with a specific STT-MRAM device variant.
xSPI MBMC v3.3.x support for FPGA and ASIC targets
This memory controller IP has been ported to, and physically tested on, a broad range of FPGA device variants, including:
- Most modern Intel FPGA device families, including:
- Intel MAX 10 – Up to 200 MHz DDR
- Cyclone IV
- Cyclone 10 LP – Up to 200 MHz DDR
- Cyclone 10 GX – Up to 250 MHz DDR
- Cyclone V
- Cyclone V SoC
- Arria 10 – Up to 250 MHz DDR
- Arria 10 SoC – Up to 250 MHz DDR
- Stratix 10 – Up to 250 MHz DDR
- Most modern Xilinx FPGA device families, including:
- Zynq 7000
- Kintex Ultrascale+
- Zynq Ultrascale+
- Virtex Ultrascale+ (ideal for supporting ASIC design prototyping in FPGA)
- Microchip (Microsemi)
- PolarFire FPGA – Up to 250 MHz DDR
Other FPGA device families may be available on request. Please contact SLL at firstname.lastname@example.org with details about the specific currently unsupported FPGA device family that you would like to use.
This memory controller IP is also currently being ported from FPGA to standard cell ASIC at up to 250 MHz DDR with x4/x8/x16 datapath support.
xSPI MBMC v3.3.x Capabilities
- Includes tight integration with all the major FPGA vendor’s graphical system integration tools (Platform Designer, Vivado, …)
- Features high quality local interconnect, with support for the following interconnect protocols:
- ARM AMBA AXI4 protocol
- ARM AMBA APB3 protocol
- Intel Avalon-MM protocol
- other interconnect protocols available on request…
- Includes internal clock-crossing circuitry between the local bus interconnect and the external memory channel to reduce circuit area and improve the performance of the customer’s design
- Excellent memory access performance for both latency sensitive and bandwidth intensive applications:
- The round trip time for read memory transfer requests through the memory controller has been optimized for latency sensitive applications, such as processor cores.
- The memory controller supports long burst memory transfer requests over the memory channel to sustain high effective memory bandwidth (>90% efficiency of memory channel)
- Note: SLL offers a range of cache technologies to significantly increase the performance of processor cores that do not have internal instruction and/or data caches when accessing external memories.
- Features low circuit area and low SRAM usages, making SLL’s memory controller viable for use in resource constrained designs.
- Includes optional support for automatic configuration of memory devices at power on:
- FPGA customers typically use the automatic configuration option
- This dramatically simplifies integration of SLL’s memory controller in customer designs, enabling all firmware to be executed in place from x8 NOR Flash.
- Include support for manual configuration of the memory controller and any attached memory devices
- ASIC customers typically use the manual configuration option
- ASIC customers can prototype their designs in FPGA with manual configuration option enabled
- Supports x4, x8 and x16 data path width in a single instantiation of SLL’s memory controller IP
- Supports 2 or more instantiations of the memory controller IP in one project
- Preliminary support for splitting AXI4 requests across 2 instances of the memory controller in parallel to double memory bandwidth is now available
xSPI MBMC v3.3.x markets, applications and use cases
Customers include industrial consortia, high profile government scientific organisations, universities, Fortune Global 500’s down to SME’s around the globe, from USA to China. Applications include commercial and industrial projects and products, such as: Sensors, video, industrial automation, medical, transport, photonics, … Use cases include: eXecution in Place (XiP) of software, long burst DMA access, video frame buffering, packet buffering, …
xSPI MBMC v3.3.x support for Everspin memory devices
SLL’s memory controller already supports, and will be physically qualified with, a broad range of Everspin memory device variants:
xSPI MBMC v3.3.x support for Commercial-off-the-shelf (COTS) boards
SLL has the broadest range of xSPI and xSPI-like board partners in this memory controller market. SLL has also tested our memory controller on the broadest range of COTS and proprietary boards in the market.
SLL leverages our close relationships to deliver known-working reference designs with free trial copies of xSPI MBMC v3.3.x (that do not expire) to: (a) reduce your project risk; and (b) get you to market faster. SLL’s board partners include:
SLL has also run our memory controller IP on boards from other board vendors such as:
Notice to Hardware Developers using xSPI MBMC v3.3.x
- Please validate your pin-mapping and PCB Layout for you selected memory devices with Synaptic Laboratories at email@example.com before manufacturing your first prototype to reduce risks.
- Please email firstname.lastname@example.org for SLL’s guidance with regard to supporting specific FPGA device families.