xSPI Multiple Bus Memory Controller (xSPI-MBMC) v3.3.x

Product page​ for

HYPERRAM™ 2.0 with HyperBus and xSPI interfaces, SEMPER™ NOR Flash with HyperBus and xSPI interfaces

SLL is an Infineon Associated Partner

SLL Partners and Supported FPGA Vendors for Infineon memory devices

Overview of xSPI MBMC IP v3.3.x support for Infineon memory devices

SLL’s xSPI Multiple Bus Memory Controller IP supports Infineon x8 HYPERRAM 2.0 and Infineon x8 SEMPER NOR Flash. 

Infineon’s HYPERRAM™ 2.0 PSRAM memory, is Infineon’s second generation of high-speed, low-pin-count, low-power, self-refresh Dynamic RAM (DRAM) for high-performance embedded systems requiring expansion memory. HYPERRAM™ 2.0 delivers upto 400 MB/s throughput and supports both HYPERBUS™ and Octal xSPI interfaces that draw upon the legacy features of both parallel and serial interface memories, while enhancing system performance and ease of design, as well as reducing system cost. 

Infineon HYPERRAM 2.0 device variants offer up to 256 Mbit of storage capacity, up to 200 MHz DDR clock speeds, with x8 data path widths.  

Infineon SEMPER™ NOR Flash is Infineon’s latest generation of NOR Flash.  It delivers upto 400 MB/s throughput and supports both HYPERBUS™ (xSPI profile 2.0) and Octal xSPI interfaces (xSPI profile 1.0).  The SEMPER™ NOR Flash memory family is Infineon’s high-performance, safe, and reliable NOR Flash solution that integrates critical safety features for a broad range of applications spanning automotive, industrial, communications, and more. With SEMPER™ NOR Flash memory, Infineon delivers the industry’s fi­rst ASIL-B compliant and ASIL-D ready NOR Flash device.

SLL’s is Infineon’s official partners for memory controller IP.  SLL works closely with Infineon to ensure SLL’s memory controller is physically qualified with many Infineon memory device variants, significantly reducing your project’s risks.

SLL’s small MBMC IP enables you to easily evaluate, select and adopt the benefits of Infineon’s latest memories in your projects and products.

SLL provides world class pre-sales and post-sales technical support for Infineon and all the major memory FPGA vendors, helping you navigate the rapidly evolving market, on the platform of your choice.

Get to market faster, with lower power consumption, lower pin count, lower cost, and far lower project risk by using SLL’s memory controller in your project/s with Infineon’s memory devices.

xSPI MBMC v3.3.x support for FPGA and ASIC targets

This memory controller IP has been ported to, and physically tested on, a broad range of FPGA device variants, including:

  • Most modern Intel FPGA device families, including:
    • Intel MAX 10 – Up to 200 MHz DDR
    • Cyclone IV 
    • Cyclone 10 LP – Up to 200 MHz DDR
    • Cyclone 10 GX – Up to 250 MHz DDR
    • Cyclone V
    • Cyclone V SoC
    • Arria 10 – Up to 250 MHz DDR
    • Arria 10 SoC – Up to 250 MHz DDR
    • Stratix 10 – Up to 250 MHz DDR
  • Most modern Xilinx FPGA device families, including:
    • Artix-7
    • Kintex-7
    • Virtex-7
    • Zynq 7000
    • Kintex Ultrascale+
    • Zynq Ultrascale+
    • Virtex Ultrascale+ (ideal for supporting ASIC design prototyping in FPGA)
  • Microchip (Microsemi)
    • PolarFire FPGA – Up to 250 MHz DDR

Other FPGA device families may be available on request. Please contact SLL at info@synaptic-labs.com with details about the specific currently unsupported FPGA device family that you would like to use.

This memory controller IP is also currently being ported from FPGA to standard cell ASIC at up to 250 MHz DDR with x4/x8/x16 datapath support.

xSPI MBMC v3.3.x Free Trials

To request a free trial for selected FPGA device families, please visit here.

xSPI MBMC v3.3.x Capabilities

  • Includes tight integration with all the major FPGA vendor’s graphical system integration tools (Platform Designer, Vivado, …)  
  • Features high quality local interconnect, with support for the following interconnect protocols:
    • ARM AMBA AXI4 protocol
    • ARM AMBA APB3 protocol
    • Intel Avalon-MM protocol
    • other interconnect protocols available on request…
  • Includes internal clock-crossing circuitry between the local bus interconnect and the external memory channel to reduce circuit area and improve the performance of the customer’s design
  • Excellent memory access performance for both latency sensitive and bandwidth intensive applications:
    • The round trip time for read memory transfer requests through the memory controller has been optimized for latency sensitive applications, such as processor cores.
    • The memory controller supports long burst memory transfer requests over the memory channel to sustain high effective memory bandwidth (>90% efficiency of memory channel)
    • Note:  SLL offers a range of cache technologies to significantly increase the performance of  processor cores that do not have internal instruction and/or data caches when accessing external memories.
  • Features low circuit area and low SRAM usages, making SLL’s memory controller viable for use in resource constrained designs. 
  • Includes optional support for automatic configuration of memory devices at power on:
    • FPGA customers typically use the automatic configuration option
    • This dramatically simplifies integration of SLL’s memory controller in customer designs, enabling all firmware to be executed in place from x8 NOR Flash.  
  • Include support for manual configuration of the memory controller and any attached memory devices
    • ASIC customers typically use the manual configuration option
    • ASIC customers can prototype their designs in FPGA with manual configuration option enabled
  • Supports x4, x8 and x16 data path width in a single instantiation of SLL’s memory controller IP
  • Supports 2 or more instantiations of the memory controller IP in one project
    • Preliminary support for splitting AXI4 requests across 2 instances of the memory controller in parallel to double memory bandwidth is now available

xSPI MBMC v3.3.x markets, applications and use cases

Customers include industrial consortia, high profile government scientific organisations, universities, Fortune Global 500’s down to SME’s around the globe, from USA to China.   Applications include commercial and industrial projects and products, such as:  Sensors, video, industrial automation, medical, transport, photonics, …   Use cases include:  eXecution in Place (XiP) of software, long burst DMA access, video frame buffering, packet buffering, …

xSPI MBMC v3.3.x support for Infineon memory devices

SLL’s memory controller supports, and is physically qualified with, a broad range of Infineon memory device variants:

  • Infineon x8 HYPERRAM 2.0 with HyperBus interface (xSPI Profile 2.0)
  • Infineon x8 HYPERRAM 2.0 with xSPI interface (xSPI Profile 1.0)
  • Infineon x8 SEMPER NOR Flash with HyperBus interface (xSPI Profile 2.0)
  • Infineon x8 SEMPER NOR Flash with HyperBus interface (xSPI Profile 1.0)

xSPI MBMC v3.3.x support for Infineon HyperRAM 2.0 with HyperBus Interface

Status of Infineon HYPERRAM 2.0 memory device testing and qualification performed by SLL: 

  • Infineon Technologies AG – HYPERRAM 2.0 with HyperBus Interface
    • Physically validated:
      • S27KS0642GABHI02  ES /  7KS0642GAHIO2  ES (   64 Mbit, 1.8V)
      • S70KS1282GABHI02  ES /  7KS1282GAHV02  ES (128 Mbit, 1.8V)
    • Physically validated on Trenz board:
      • S70KS1282GABHV020 (128 Mbit, 1.8V)
    • Physical validation in process on Trenz board:
      • S70KL1282GABHV020 (128 Mbit, 3V)
    • Validated in simulator:
      • Pending..

xSPI MBMC v3 support for Infineon HyperRAM 2.0 with Octal Interface

Status of Infineon HYPERRAM 2.0 memory device testing and qualification performed by SLL:

  • Infineon Technologies AG – HYPERRAM 2.0 with Octal Interface
    • Physically validated:
      • Pending..
    • Physical validation in process on Trenz board:
      • S27KS0643GABHI020  (  64 Mbit, 1.8V)
      • S70KL1283GABHV020  (128 Mbit, 3V)
      • S27KL128DPBHV020    (128 Mbit, 3V)
    • Validated in simulator:
      • Pending..

xSPI MBMC v3.3.x support for Infineon SemperFlash with Octal Interface

Status of Infineon SemperFlash memory device testing and qualification performed by SLL:

  • Infineon Technologies AG – Semper Flash with Octal Interface
    • Physically validated:
      • S26HS512TGABHI00 /  26HS512TAI00 (512 Megabit, 1.8V)
    • Physical validation in process
      • S26HL512TFPBHI01  / 26HL512TPIO1 (512 Megabit 3.0V)
    • Physical validation in process on Trenz Board:
      • S28HS512TGABHB010  (512 Mbit, 1.8V)
      • S28HL01GTFPBHV030 ( 1 Gigabit, 3V)
      • S28HS01GTFPBHI030  ( 1 Gigabit, 1.8V)
    • Physical qualification available on customer demand
      • S26HS01GT (1 Gigabit, 1.8V)
      • S26HL01GT (1 Gigabit, 3.0V)

xSPI MBMC v3.3.x support for Infineon SemperFlash with HyperBus Interface (HyperFlash 2.0)

Status of Infineon SemperFlash memory device testing and qualification performed by SLL:

  • Infineon Technologies AG – Semper Flash with HyperBus Interface (HyperFlash 2.0)
    • Physically validated:
      • S26HS512TGABHI00 /  26HS512TAI00 (512 Megabit, 1.8V)
    • Physical validation in process
      • S26HL512TFPBHI01  / 26HL512TPIO1 (512 Megabit 3.0V)
    • Physical validation in process on Trenz board:
      • S26HL512TFPBHM010      (512 Megabit, 3V)
      • S26HL01GTFPBHI030       (1 Gigabit, 3V)
      • S26HS01GTGABHV030    (1 Gigabit, 1.8V)
    • Physical qualification available on customer demand
      • S26HS01GT (1 Gigabit, 1.8V)
      • S26HL01GT (1 Gigabit, 3.0V)

xSPI MBMC v3.3.x support for Commercial-off-the-shelf (COTS) boards

SLL has the broadest range of xSPI and xSPI-like board partners in this memory controller market.  SLL has also tested our memory controller on the broadest range of COTS and proprietary boards in the market.

SLL leverages our close relationships to deliver known-working reference designs with free trial copies of xSPI MBMC v3.3.x (that do not expire) to:  (a) reduce your project risk; and (b) get you to market faster.  SLL’s board partners include:

SLL has also run our memory controller IP on boards from other board vendors such as:

Notice to Hardware Developers using xSPI MBMC v3.3.x

  • Please validate your pin-mapping and PCB Layout for you selected memory devices with Synaptic Laboratories at info@synaptic-labs.com before manufacturing your first prototype to reduce risks.
  • Please email info@synaptic-labs.com for SLL’s guidance with regard to supporting specific FPGA device families.

Infineon HyperRAM 2.0 with Octal Interface Resources

  • Standards
  • Application notes and other guidance:
    • Semper Access Program
      • Most of the product guidance and application notes can only be accessed by enrolling in the Semper Access Program
    • AN224153 – Design and Layout Guide for Semper Flash Memory
      • Requires enrolment with Semper Access Program
    • Product selector guide for HyperRAM 2.0 with Octal SPI Interface
  • Data sheets:

Infineon SemperFlash with Octal Interface Resources

Infineon Semper NOR Flash with HyperBus interface has conformance with JEDEC xSPI Profile 1.0:

Contact SLL for information on many development board options for all these memory vendors xSPI memory devices: info@synaptic-labs.com