xSPI Multiple Bus Memory Controller (xSPI-MBMC) v3.3.x

Product page​ for

HyperRAM™ 1.0, 2.0 and 3.0 memory devices and OctalNAND memory devices

SLL is Winbond’s partner for memory controller and related technologies.

SLL Partners and Supported FPGA Vendors for Winbond memory devices

Overview of xSPI MBMC IP v3.3.x support for Winbond memory devices

SLL’s xSPI Multiple Bus Memory Controller IP supports Winbond HyperRAM 1.0, 2.0 and 3.0 and soon Winbond OctalNAND.

Winbond HyperRAM memories offer good performance with lower hardware and power costs.  HyperRAM device variants offer up to 512 Mbit of storage capacity, up to 250 MHz DDR clock speeds, with x8 or x16 data path widths, and a wide range of package options including 4mm x 4mm BGA49 and tiny WLCSP footprints.  

SLL’s is Winbond’s official partners for memory controller IP.  SLL works closely with Winbond to ensure SLL’s memory controller is physically qualified with many Winbond memory device variants, significantly reducing your project’s risks.

SLL’s small xSPI MBMC IP enables you to easily evaluate, select and adopt the benefits of Winbond’s latest memories in your projects and products.

SLL provides world class pre-sales and post-sales technical support for Winbond and all the major memory FPGA vendors, helping you navigate the rapidly evolving market, on the platform of your choice.

Get to market faster, with lower power consumption, lower pin count, lower cost, and far lower project risk by using SLL’s memory controller in your project/s with Winbond’s memory devices.

xSPI MBMC v3.3.x support for Winbond memory devices

SLL’s memory controller supports, and is physically qualified with, a broad range of Winbond memory device variants:

  • Supports Winbond x8 HyperRAM 1.0 and x8 HyperRAM 2.0
    (low power replacement for SDR, LPSDR, DDR and CellularRAM)
  • Supports Winbond x16 HyperRAM 3.0
  • Support for Winbond Octal NAND Flash coming soon
    (for low-cost per bit and largest storage capacities)

xSPI MBMC IP v3.3.x estimated effective bandwidth for PSRAM memories

For all DDRx SDRAM and PSRAM devices, the effective memory bandwidth is always less than the wire speed.  The estimated effective memory bandwidth of your application using PSRAM devices depends on:

  • The data path width of the memory channel (x8, x16, ..)
  • The memory channel clock speed (ideally the highest speed supported by the memory device and SLL’s memory controller IP for that FPGA device family)
  • The initial access latency (ideally the lowest value permitted by the PSRAM device for a given clock speed)
  • The burst length of memory transfer requests issued to SLL’s memory controller IP (ideally 64 bytes or higher to PSRAM)
  • The number of concurrently outstanding memory transfer requests issued to SLL’s memory controller IP (ideally 2)
  • The temperature grade of the memory device (higher temperature grades must self REFRESH more often, resulting in shorter maximum burst lengths)

Use SLL’s estimated effective bandwidth calculator below to find the optimal burst length(s) for your application’s use-case when using SLL’s memory controller below with a specific PSRAM device variant.

Generally speaking, SLL recommends 1.8V devices for use with most FPGA to reduce power consumption, and in some cases, increase the top clock speed of the memory channel.

xSPI MBMC v3.3.x support for FPGA and ASIC targets

This memory controller IP has been ported to, and physically tested on, a broad range of FPGA device variants, including:

  • Most modern Intel FPGA device families, including:
    • Intel MAX 10 – Up to 200 MHz DDR
    • Cyclone IV 
    • Cyclone 10 LP – Up to 200 MHz DDR
    • Cyclone 10 GX – Up to 250 MHz DDR
    • Cyclone V
    • Cyclone V SoC
    • Arria 10 – Up to 250 MHz DDR
    • Arria 10 SoC – Up to 250 MHz DDR
    • Stratix 10 – Up to 250 MHz DDR
  • Most modern Xilinx FPGA device families, including:
    • Artix-7
    • Kintex-7
    • Virtex-7
    • Zynq 7000
    • Kintex Ultrascale+
    • Zynq Ultrascale+
    • Virtex Ultrascale+ (ideal for supporting ASIC design prototyping in FPGA)
  • Microchip (Microsemi)
    • PolarFire FPGA – Up to 250 MHz DDR

Other FPGA device families may be available on request. Please contact SLL at info@synaptic-labs.com with details about the specific currently unsupported FPGA device family that you would like to use.

This memory controller IP is also currently being ported from FPGA to standard cell ASIC at up to 250 MHz DDR with x4/x8/x16 datapath support.

xSPI MBMC v3.3.x Free Trials

To request a free trial for selected FPGA device families, please visit here.

xSPI MBMC v3.3.x Capabilities

  • Includes tight integration with all the major FPGA vendor’s graphical system integration tools (Platform Designer, Vivado, …)  
  • Features high quality local interconnect, with support for the following interconnect protocols:
    • ARM AMBA AXI4 protocol
    • ARM AMBA APB3 protocol
    • Intel Avalon-MM protocol
    • other interconnect protocols available on request…
  • Includes internal clock-crossing circuitry between the local bus interconnect and the external memory channel to reduce circuit area and improve the performance of the customer’s design
  • Excellent memory access performance for both latency sensitive and bandwidth intensive applications:
    • The round trip time for read memory transfer requests through the memory controller has been optimized for latency sensitive applications, such as processor cores.
    • The memory controller supports long burst memory transfer requests over the memory channel to sustain high effective memory bandwidth (>90% efficiency of memory channel)
    • Note:  SLL offers a range of cache technologies to significantly increase the performance of  processor cores that do not have internal instruction and/or data caches when accessing external memories.
  • Features low circuit area and low SRAM usages, making SLL’s memory controller viable for use in resource constrained designs. 
  • Includes optional support for automatic configuration of memory devices at power on:
    • FPGA customers typically use the automatic configuration option
    • This dramatically simplifies integration of SLL’s memory controller in customer designs, enabling all firmware to be executed in place from x8 NOR Flash.  
  • Include support for manual configuration of the memory controller and any attached memory devices
    • ASIC customers typically use the manual configuration option
    • ASIC customers can prototype their designs in FPGA with manual configuration option enabled
  • Supports x4, x8 and x16 data path width in a single instantiation of SLL’s memory controller IP
  • Supports 2 or more instantiations of the memory controller IP in one project
    • Preliminary support for splitting AXI4 requests across 2 instances of the memory controller in parallel to double memory bandwidth is now available

xSPI MBMC v3.3.x markets, applications and use cases for PSRAM

Customers include industrial consortia, high profile government scientific organisations, universities, Fortune Global 500’s down to SME’s around the globe, from USA to China.   Applications include commercial and industrial projects and products, such as:  Sensors, video, industrial automation, medical, transport, photonics, …   Use cases include:  execution of software, long burst DMA access, video frame buffering, packet buffering, …

xSPI MBMC v3.3.x support for Commercial-off-the-shelf (COTS) boards

SLL has the broadest range of xSPI and xSPI-like board partners in this memory controller market.  SLL has also tested our memory controller on the broadest range of COTS and proprietary boards in the market.

SLL leverages our close relationships to deliver known-working reference designs with free trial copies of xSPI MBMC v3.3.x (that do not expire) to:  (a) reduce your project risk; and (b) get you to market faster.  SLL’s board partners include:

SLL has also run our memory controller IP on boards from other board vendors such as:

Notice to Hardware Developers using xSPI MBMC v3.3.x

  • Please validate your pin-mapping and PCB Layout for you selected memory devices with Synaptic Laboratories at info@synaptic-labs.com before manufacturing your first prototype to reduce risks.
  • Please email info@synaptic-labs.com for SLL’s guidance with regard to supporting specific FPGA device families.

Winbond HyperRAM 1.0 Resources

Winbond HyperRAM 2.0 Resources

Winbond Octal NAND resources

  • Winbond
  • Standards
    • None.
  • Application notes and other guidance
  • Datasheets / product pages
    • W35N01JW    (1024 Mbit, 1.8V)
      • W35N01JWTBIG    / 35N01JWTBIG
      • W35N01JWTBIT    / 35N01JWTBIT
      • W35N01JWTBAG  / 35N01JWTBAG 
      • W35N01JWTBAT  / 35N01JWTBAT
    • W35N02JW    (2048 Mbit, 1.8V)
      • W35N02JWTBIG
    • W35N04JW    (4096 Mbit, 1.8V)
      • W35N02JWTBIG 

Contact SLL for information on many development board options for all these memory vendors xSPI memory devices: info@synaptic-labs.com