SLL Multi Bus Memory Controller (MBMC) IP

for HyperBus 1.0, HyperBus 2.0, OctaBus, and Xccela Bus

SLL’s new Multiple Bus Memory Controller (MBMC) IP:
  • Multiple protocol, multiple vendor support, in SLL’s unified MBMC IP
    • This reduces your project’s risk by ensuring multiple sourcing options for your long term memory supplies
  • Physically tested with over 40 different memory devices:
    • AP Memory® Xccela™ PSRAM and OctaRAM
    • Cypress Semiconductor® (Cypress) HyperRAM™ 1.0 and HyperFlash™ 1.0 and HyperMCP 1.0
    • Cypress HyperRAM 2.0 and HyperFlash 2.0 (Semper Flash with HyperBus interface)
    • Integrated Silicon Solution Inc.® (ISSI)  HyperRAM 1.0 (single die and dual die), HyperFlash 1.0
    • ISSI OctalRAM (coming soon)
    • Jeju Semiconductor Corp® (JSC) OctaRAM
    • Winbond HyperRAM 1.0 and 2.0
    • JEDEC xSPI Profile 1.0 (coming soon)
  • Supports memory channels running at up to 200 MHz on many FPGA device families
  • Supports 2 or more instantiations of memory controller IP in one FPGA design
  • Support for 16-bit wide PSRAM data path coming soon
  • You can find a wide range of HyperBus and CRUVI Boards from our board partners below.
  • Supports Intel FPGA, Microchip FPGA and Xilinx FPGA (see below)
  • Is based on SLL’s proven HyperBus Memory Controller (HBMC) IP for HyperBus 1.0 devices
    • Bundled with the Intel® Cyclone® 10 LP Evaluation Kit sold by Intel here, and by all Intel distributors (Arrow, Digi-Key, Magnica, etc)
    • Customers include industrial consortia, high profile government scientific organisations, universities, Fortune Global 500’s down to SME’s around the globe, from USA to China. 
  • Applications Include commercial and industrial projects and products:
    • Sensors, video, visioning, industrial automation, medical, transport, photonics, …
  • Transition easily from HyperBus 1.0 to HyperBus 2.0:
    • SLL HyperBus 1.0 customers are already successfully employing 200 MHz HyperBus 2.0 devices using SLL’s IP  
  • To request a free trial, please email:  info@synaptic-labs.com
SLL MBMC supports 8-, 16- and 32-bit datapaths
to address a broad range of use-cases, including:
16-bit tightly coupled PSRAM memory channel:
  • MBMC 2.0 supports accessing two PSRAM devices in parallel to double the wire speed memory bandwidth
  • Ideal for video frame applications
Up to four independent x8 memory channels in one FPGA design:
  • Each soft processor core can have its own private memory subsystem for optimal performance and determinism
Interleaved memory access across multiple PSRAM memory channels:
  • Create a 16-bit channel using 2 interleaved x8 channels  (preliminary support available for AXI4)
  • Create a 32-bit channel using 4 interleaved x8 channels  (preliminary support available for AXI4)
  • Create a 32-bit channel using 2 interleaved x16 channels (under development)
SLL is collaborating with Cypress and Intel on
Active Serial configuration of Intel FPGA devices
using “Semper NOR Flash with HyperBus Interface”

This will enable the Semper Flash device used for configuration of the FPGA to then be accessed with high bandwidth from within the FPGA fabric. The performance of  “Semper Flash with HyperBus Interface”  devices is very similar to PSRAM at a given clock speed, permitting execution of code in place from SemperFlash.

Contact us on info@synaptic-labs.com to explore the benefits of replacing very slow EPCQ/QSPI configuration flash with fast Semper Flash with RE-USE of the fast Semper Flash across FPGA designs.

Developer resources
  • Please validate your pin-out and board design with Synaptic Labs, your FPGA vendor, and your memory vendors before manufacturing your first prototype.
    • Please contact Synaptic Laboratories at info@synaptic-labs.com to validate the memory channel pin-outs for your specific FPGA device before manufacture.
  • Please contact AP Memory at  enquiry@apmemory.com  for:
    • Xccela PSRAM data sheets
    • OctaRAM data sheets
    • AP Memory, “OPI 24B/90B board design guide”, 5 March 2019.
SLL Partners
MBMC has been ported to several Intel FPGA device families

Starting from around 400 4-to-1 logic elements, SLL’s MBMC is many times smaller than any DDRx SDRAM controller IP available for Intel FPGA.  Furthermore, x8 PSRAM requires approximately 3x less pins than x8 DDRx, making it ideal in resource constrained designs.

Memory channel clock speeds:
  • Supports full 200 MHz @ 1.8v and 133 MHz @ 3.0v clock speeds on:
    • All Cyclone 10 GX, Arria 10, Arria 10 SoC. 
  • Supports up to 200 MHz @  1.8V on some Cyclone 10 LP
    • Targeting 180-to-200 MHz @  1.8V on all Cyclone 10 LP devices
  • Targeting 180-to-200 MHz @  1.8V on all MAX 10 devices
  • Supports around 140 to 150 MHz @ 1.8V on Cyclone V and Cyclone V SoC

Additional features:
  • Automatically configures PSRAM and NOR Flash devices at power on
  • Memory devices immediately available for read/write access without a customer boot loader.
  • Internal clock-crossing logic to reduce circuit area of customer’s design.
  •  
MBMC IP has been ported to Microsemi PolarFire FPGA

SLL is Microchip’s chosen vendor to support up to 200 MHz HyperBus, OctaRAM and Xccela PSRAM devices on Microsemi PolarFire devices

MBMC IP is complementary to PolarFire’s DDRx solutions:
  • Up to 200 MHz memory channel at 1.8V
  • Up to 133 MHz memory channel at 3.0V
  • Supports AXI4 interface
  • Supports GUI configuration in Libero
  • Up to 19x less FPGA Logic Elements (LE) than x16 DDR3L controller
  • Up to 5x less FPGA I/O pins than x16 DDR3L
  • Up to 4x less FPGA I/O pins than x8 DDR3L
  • RISC-V software performance on 8-bit PSRAM @ 200 MHz is highly competitive with 16-bit DDR3 @ 333 MHz
  • Automatically configures memory devices at power on
  • Immediately available for read/write access without a customer boot loader
  • Internal clock-crossing logic to reduce circuit area of customer’s design.

Contact us at info@synaptic-labs.com to enrol for the Beta under our Early Access Program.

MBMC IP has been ported to Xilinx Series-7 devices
  • SLL has physically tested MBMC IP on several Artix-7, Spartan-7 and And Zynq-7000 boards from Trenz Electronic GmbH.
  • Supports AXI4 interface
  • Supports GUI configuration in Vivado
  • Automatically configures memory devices at power on
  • Memory devices immediately available for read/write access without a customer boot loader.
  • Synaptic Labs is working on upgrading our IP to support up to 200 MHz on Series-7 devices.
SLL can port our MBMC IP to support Efinix Trion FPGA

Please contact SLL on info@synaptic-labs.com to register your interest with regard to MBMC IP support on Efinix FPGA devices.

SLL can port our MBMC IP to Lattice FPGA

Including:

  • Lattice MachXO2 FPGA
  • and other Lattice FPGA devices.

 

Please contact SLL on info@synaptic-labs.com to register your interest with regard to MBMC IP support on one or more Lattice FPGA devices.

Please contact SLL on info@synaptic-labs.com to learn about the use of our IP in standard cell ASIC designs.

Status of AP Memory Xccela PSRAM device testing and qualification performed by SLL (as of January 2020):
  • AP Memory – Xccela PSRAM:
    • Physically validated:
      • APS6408L‐OBx  (64 Mbit, 1.8V)
      • APS12808L-OBx (128 Mbit, 1.8V)
    • Validated in simulator:
      • APS3208L-OBx (32 Mbit, 1.8V)
      • APS3208L-3OBx (32 Mbit, 3.0V)
      • APS6408L-3OBx (64 Mbit, 3.0V)
      • APS12808L-3OB (128 Mbit, 3.0V)
      • APS25608N-OBRx  (256 Mbit, 1.8V)
      • APS51208N-OBRx (512 Mbit, 1.8V)
Status of AP Memory OctaRAM device testing and qualification performed by SLL (as of January 2020):
  • AP Memory – OctaRAM:
    • Physically validated:
      • APM6408L-OC (64 Mbit, 1.8V)
      • APM6408L-3OC (64 Mbit, 3.0V)
    • Support planned:
      • APS25608N‐OCx (256 Mbit, 1.8V)
      • APS51208N‐OCx (512 Mbit, 1.8V)
Status of Cypress HyperFlash device testing and qualification performed by SLL (as of January 2020):
  • Cypress Semiconductor Corporation  – HyperFlash 1.0
    • Physically validated:
      • S26KS512SDPBHI020 / 6KS512SDPHIO2 (512 Mbit, 1.8V)
    • Validated in the simulator:
      • S26KS128S (128 Mbit, 1.8V)
      • S26KL128S (128 Mbit, 3.0V)
      • S26KL256S (256 Mbit, 1.8V)
      • S26KL512S (256 Mbit, 3.0V)
      • S26KS256S (512 Mbit, 1.8V)
      • S26KS512S (512 Mbit, 3.0V)
Status of Cypress HyperRAM 1.0 device testing and qualification performed by SLL (as of January 2020): 
  • Cypress Semiconductor Corporation –  HyperRAM 1.0
    • Physically validated:
    • Validated in simulator:
      • S27KS0641 (  64 Mbit, 1.8V)
      • S27KL0641 (  64 Mbit, 3.0V)
      • S70KS1281 (128 Mbit, 1.8V)
Status of Cypress HyperMCP 1.0 device testing and qualification performed by SLL (as of January 2020):
Status of Cypress “Semper NOR Flash with HyperBus interface” (HyperFlash 2.0) memory device testing and qualification performed by SLL (as of January 2020):
  • Cypress Semiconductor Corporation – Semper Flash with HyperBus Interface
    • Physically validated:
      • S26HS512TGABHI00 /  26HS512TAI00 (512 Megabit, 1.8V)
    • Physical validation in process
      • S26HL512TFPBHI01  / 26HL512TPIO1 (512 Megabit 3.0V)
    • Physical qualification available on customer demand
      • S26HS01GT (1 Gigabit, 1.8V)
      • S26HL01GT (1 Gigabit, 3.0V)
  • Cypress Semiconductor Corporation – Semper Flash with Octal Interface
    • Physically validated:
      • S26HS512TGABHI00 /  26HS512TAI00 (512 Megabit, 1.8V)
    • Physical validation in process
      • S26HL512TFPBHI01  / 26HL512TPIO1 (512 Megabit 3.0V)
    • Physical qualification available on customer demand
      • S26HS01GT (1 Gigabit, 1.8V)
      • S26HL01GT (1 Gigabit, 3.0V)
Status of Cypress HyperRAM 2.0 memory device testing and qualification performed by SLL (as of February 2020): 
  • Cypress Semiconductor Corporation – HyperRAM 2.0 with HyperBus Interface
    • Physically validated:
      • S27KS0642GABHI02  ES /  7KS0642GAHIO2  ES (   64 Mbit, 1.8V)
      • S70KS1282GABHI02  ES /  7KS1282GAHV02  ES (128 Mbit, 1.8V)
    • Validated in simulator:
      • Pending..
  • Cypress Semiconductor Corporation – HyperRAM 2.0 with Octal Interface
    • Physically validated:
      • Pending..
    • Validated in simulator:
      • Pending..
Status of ISSI HyperFlash 1.0 device testing and qualification performed by SLL (as of December 2019):
Status of ISSI HyperRAM 1.0 memory device testing and qualification performed by SLL (as of December 2019):
  • Integrated Silicon Solution Inc. (ISSI) –  HyperRAM 1.0
    • Physically validated:
      • IS66WVH8M8ALL-166 (64 Mbit, 1.8V)
      • IS66WVH8M8DALL-100 (64 Mbit, 3.0V)
      • IS66WVH16M8ALL-166 (128 Mbit, dual die, 1.8V)
    • Pending physical validation:
      • IS66WVH32M8DALL-166B1L1  (256 Megabit, single die, 1.8V)
    • Provisional support available on customer demand
      • IS67WVH8M8DALL             (   64 Megabit, single die, 1.8V)
      • IS67WVH8M8DBLL             (   64 Megabit, single die, 3.0V)
      • IS67WVH16M8DALL           (128 Megabit, single die, 1.8V)
      • IS66/67WVH16M8DBLL     (128 Megabit, single die, 3.0V)
      • IS66/67WVH32M8DBLL     (256 Megabit, single die, 3.0V)
      • IS66/67WVH16M8EDALL  (128 Megabit, single die, 1.8V, Internal ECC)
      • IS66/67WVH16M8EDBLL  (128 Megabit, single die, 3.0V, Internal ECC)

Status of ISSI OctalRAM device testing and qualification performed by SLL (as of January 2020):

Status of JSC OctaRAM device testing and qualification performed by SLL (as of January 2020):

  • Jeju Semiconductor Corp (JSC) – OctaRAM:
    • Physically validated:
      • JSC28SSP8AGDY-50I (128 Mbit, 1.8V) 
      • JSC64SSP8AGDY-50I (64 Mbit, 1.8V)
      • Validated in simulator:
      • JSC28SSU8AGDY-75I (128 Mbit, 3.0V)
      • JSC64SSU8AGDY-75I (64 Mbit, 3.0V)

Status of Winbond HyperBus 2.0 compatible memory device testing and qualification performed by SLL (as of December 2019):

  • Winbond –  HyperRAM 2.0
    • Validated in the Simulator
      • W956D8MBYA5I (64 Mbit, 1.8V)
      • W956D8MBYA6I (64 Mbit, 1.8V)
      • W956A8MBYA5I (64 Mbit, 3.0V)
      • W956A8MBYA5I (64 Mbit, 3.0V)
    • Support available on customer request:
      • W955D8MBYA6I (32 Mbit, 1.8V)
      • W957D8MFYA5I (128 Mbit, 1.8V)
      • W957A8MFYA5I (128 Mbit, 3.0V)
      • W957A8MFYA6I (128 Mbit, 3.0V)
Status of board testing and qualification performed by SLL (as of October 2019):
Status of board testing and qualification performed by SLL (as of October 2019):
  • Critical Link, LLC
    • Multiple Cyclone 10 GX SoM populated with ISSI HyperRAM @ 166 MHz – Validated
    • Multiple Cyclone 10 GX SoM populated with AP Memory Xccela PSRAM @ 200 MHz – Pending
Status of board testing and qualification performed by SLL (as of October 2019):
  • devboards GmbH
    • HyperMAX 25 Development Kit – Validated
    • HyperMAX 50 Development Kit – Validated
    • DBM-SoC1-Base1 with DBM-SoC1-A2 (Cyclone V SoC SE) with proprietary memory boards, each memory board populated with 4 xSPI channels, 2 memory devices per xSPI channel:
      • Populated with AP Memory Xccela PSRAM – Pending
      • Populated with Cypress HyperRAM  – Pending
      • Populated with Cypress HyperFlash  – Pending
      • Populated with ISSI HyperRAM  – Pending

 

Status of board testing and qualification performed by SLL (as of October 2019):

 

Status of board testing and qualification performed by SLL (as of October 2019):
Status of board testing and qualification performed by SLL (as of October 2019):
Status of board testing and qualification performed by SLL (as of October 2019):