xSPI Multiple Bus Memory Controller (xSPI-MBMC)

SLL’s xSPI Multiple Bus Memory Controller IP supports AP Memory IoT RAM (Xccela), IoT RAM (OctaRAM) and QSPI DDR PSRAM.

AP Memory’s range of PSRAM memories offer good performance with lower hardware and power costs. 

AP Memory IoT RAM (Xccela) device variants offer up to 512 Mbit of storage capacity, up to 200 MHz DDR clock speeds (up to 250 MHz with KGD), with x8 and x16 data path widths, and a wide range of package options including 4mm x 4mm BGA49 and tiny WLCSP footprints.  

AP Memory IoT RAM (OctaRAM) device variants offer up to 512 Mbit of storage capacity, up to 200 MHz DDR clock speeds, with x8 data path widths, and a wide range of package options including 4mm x 4mm BGA49 and tiny WLCSP footprints.  

AP Memory offer a 16 Mbit and 128 Mbit QSPI DDR SPI device with read data strobe to enable up to 166 Mbytes/s wire speed for use in pin constrained customer designs.  

SLL is one of AP Memory’s official partners for memory controller IP.  SLL works closely with AP Memory to ensure SLL’s memory controller is physically qualified with many of AP Memory’s memory device variants, significantly reducing your project’s risks.

SLL’s small MBMC IP enables you to easily evaluate, select and adopt the benefits of AP Memory’s latest memories in your projects and products.

SLL provides world class pre-sales and post-sales technical support for AP Memory and all the major memory FPGA vendors, helping you navigate the rapidly evolving market, on the platform of your choice.

Get to market faster, with lower power consumption, lower pin count, lower cost, and far lower project risk by using SLL’s memory controller in your project/s with AP Memory’s memory devices.