Fast chip to chip communications over Octa, Octal and xSPI Profile 2.0 PSRAM protocols

This SLL IP enables high-bandwidth, low latency, bidirectional chip to chip communications over Octa, Octal and xSPI memory protocols.

For Tightly coupled BIDIRECTIONAL communications between:
⚡  Your chosen ASIC microcontroller unit (MCU) ↔︎ your chosen FPGA
⚡  Your chosen ASIC microprocessor unit (MPU) ↔︎ your chosen FPGA
⚡  Your chosen FPGA’s: FPGA ↔︎ FPGA

SLL’s chip to chip peripheral:
  • IP core has been tested with OCTOSPI peripheral in STM32L4+ and STM32L5 Series MCUs
  • Is compatible with a broad range of MCU memory controllers, and:
  • Supports up to 200 MHz DDR clock speed
  • Relies on a strict subset of the PSRAM commands of JEDEC xSPI – Profile 2.0.
    • Supports xSPI burst read / write operations for high effective memory bandwidth.
    • Supports “xSPI Profile 2.0 Standard Command Modifier Format” and “xSPI Profile 2.0 Extended Command Modifier Format”.
  • Multiplexes two communications channels over the xSPI channel to enable bidirectional communications.
  • Each communications channel implements a bin-based flow control algorithm for high performance.
  • Can support most FPGA vendors device families including but not limited to:
    • Intel FPGA’s and SoC’s including Cyclone 10 LP, Max10, etc
    • Xilinx Series-7 families including UltraScale and UltraScale+
    • Standard cell ASIC
    • Send an email to with requests for support on other targets. Also for information on evaluation hardware with free trial IP.

Contact SLL for information on many development board options for all these memory vendors xSPI memory devices: