Fast chip to chip communications over octa, octal, and xSPI protocols

SLL Partners and Supported FPGA and Memory Vendors

This SLL IP enables chip to chip communications over octa / octal / xSPI protocols.
The result is high-bandwidth, low latency, bidirectional communications for ASIC microcontroller units [MCU <-> FPGA], and ASIC microprocessor units [MPU) <-> FPGA], and [FPGA <-> FPGA].

SLL’s chip to chip peripheral:
  • IP core has been tested with OCTOSPI peripheral in STM32L4+ and STM32L5 Series MCUs
  • is compatible with a broad range of MCU memory controllers, and:
    a) SLL’s xSPI Multiple Bus Memory Controller (xSPI-MBMC) IP v3.x operating in:

    i) HyperRAM(TM) 1.0 mode
    ii) HyperRAM(TM) 2.0 mode
    iii) JEDEC xSPI Profile 2.0 PSRAM mode

    b) Send an email to info@synaptic-labs.com with questions about compatibility with your preferred microcontroller unit (MCU).

  • supports up to 200 MHz DDR clock speed
  • relies on a strict subset of the PSRAM commands of JEDEC xSPI – Profile 2.0.
    a) Supports xSPI burst read / write operations for high effective memory bandwidth.
    b) Supports “xSPI Profile 2.0 Standard Command Modifier Format” and “xSPI Profile 2.0 Extended Command Modifier Format”.
  • multiplexes two communications channels over the xSPI channel to enable bidirectional communications.
  • each communications channel implements a bin-based flow control algorithm for high performance.
  • can support most FPGA vendors device families including but not limited to:
    a) Intel FPGA’s and SoC’s including Cyclone 10 LP, Max10, etc
    b) Xilinx Series-7 families including UltraScale and UltraScale+
    c) standard cell ASIC
    d) Send an email to info@synaptic-labs.com with requests for support on other targets.

Send an email to info@synaptic-labs.com to learn more about this solution.

Contact SLL for information on many development board options for all these memory vendors xSPI memory devices: info@synaptic-labs.com