SLL HyperBus Memory Controller (HBMC) IP

One IP that supports HyperRAM 1.0, HyperFlash 1.0, and Hyper Multichip (HyperMCP) memory devices from all the HyperBus 1.0 memory vendors

SLL still makes its low circuit area HBMC IP available for customers targeting Generation 1.0 HyperBus memory devices.  SLL’s reference designs for HBMC IP have been downloaded thousands of times. 

SLL continues to maintain this IP since 2016.   

SLL’s HBMC IP has been widely deployed in commercial projects and products since 2016 on a wide range of Intel, Microchip (Microsemi), and Xilinx FPGA’s.  

HBMC IP can also be ported quickly to Efinix and Lattice devices (upon request).

Synaptic Laboratories Ltd (SLL) offers tailored licensing plans, including:
Annual subscription licensing plans suitable for low-, mid-, and high production volumes

  • Free trial HBMC IP (with 10 minute run-time limiter)
  • Low cost R&D version (with generally a 24 hour run-time limiter)
  • Low cost full R&D and Production licence.
  • Licensing models are tailored to suit the customers project and timelines. Annual licensing model provides the lowest cost model.

To learn more about HBMC IP continue to read below.

NOTE:  the HBMC IP has been generally superseded by SLL’s far more advanced low circuit area Multiple Bus Memory Controller (MBMC) IP.

  • xSPI MBMC delivers superior performance
  • xSPI MBMC supports all the Generation 1.0 HyperBus devices
  • Plus all the Generation 2.0 HyperBus devices
  • Plus all the OctaBus devices
  • Plus the Xccela Bus devices.

HyperBus, OctaBus and Xccela Bus are all very similar xSPI protocols.  xSPI MBMC IP enables you to swap very easily between any of these protocols and devices. xSPI MBMC enables to select from any one of the ~9 supported memory vendors and their many different memory device options.  This includes x8 and x16 devices, tiny footprint devices, and devices with special characteristics including ECC.  Everspin is also an SLL partner for and xSPI MBMC IP will also support their exciting MRAM devices when they are released.  

xSPI MBMC delivers maximum flexibility and choice at low cost. To learn more about xSPI MBMC IP click here.

  • More information about HBMC IPIntel chose SLL’s HBMC IP to bundle with their Cyclone 10 LP Evaluation Kit. Intel and its channel partners (Arrow, Macnica, etc,) conducted training sessions using the Eval Kit and SLL’s IP in all global regions.
  • SLL is the partner of the HyperBus 1.0 memory vendors for memory controller IP.HBMC IP Performance:https://fpgacloud.intel.com/devstore/platform/17.1.0/Standard/high-bandwidth-hyperram-result-for-intels-board-test-system/

    The benefits of selecting a known and trusted HBMC IP validated widely in commercial projects

    Your project will automatically benefit (both immediately and for years into the future) from:

    • SLL’s strong ongoing partnerships with Intel, Cypress, ISSI, and various development board makers who have standardised on SLL’s HBMC IP
    • The input received from commercial customers that have already proven and selected our IP from around the world
    • SLL’s domain expertise
    • SLL’s role as the domain expert intermediary between our hardware partners and our customers.  We receive rapid support from all our partners for all our customers.


    Why you should choose Cypress and/or ISSI HyperBus 1.0 memories with Intel FPGAʼs and Synaptic Labs’ proven HBMC IP ?

HyperBus 1.0 memories are targeted for Space Weight and Power (SWaP) sensitive applications.

They are also available in multi chip packages (HyperMCP):
  • The 48 mm² 24-Ball BGA Cypress multi-chip package (MCP) (http://www.cypress.com/HyperFlashHyperRAMMCPPSG) incorporates 64 Mbit HyperRAM and up to 512 Mbit HyperFlash
  • Requires up to 70% less pins and up to 77% less footprint then existing SDRAM and Quad SPI memory solutions
  • Up to 280 Megabytes/s throughput (512 byte long bursts on 150 MHz HyperRAM)
  • HyperFlash read access has similar performance to HyperRAM read access
  • Power up instantly by rapidly delivering boot and application code stored in the NOR Flash memory to the Nios II core
  • Nios II software performance on HyperRAM and HyperFlash @ 150 MHz is:-
  • Highly competitive with 16-bit DDR3 @ 333 MHz
  • Up to ~1.5x faster than 16-bit SDR SDRAM @ 100 MHzGetting started on HyperRAM 1.0, HyperFlash 1.0 and HyperMCP 1.0 memories today is simple and low cost. There are many free reference designs available from SLL for a wide range of Intel, Xilinx and Microchip (Microsemi) FPGA’s. Intel also makes SLL reference designs available from the Intel website. There are many low cost COTS development board options: – There is a range of COTS low cost development boards standardised on SLL’s HBMC IP for Generation 1.0 HyperRAM and HyperFlash. Examples include:
  • Intel Cyclone® 10 LP eval kit board (https://www.altera.com/products/boards_and_kits/dev-kits/altera/cyclone-10-lp-evaluation-kit.html) with HyperRAM
  • Aries Embedded (https://www.aries-embedded.com/system-on-module/fpga/cyclone-10lp-intel-fpga-mcxl-som-low-power-cost-sensitive)®
  • Trenz Electronics offers wide range of board options.Visit our Partners page to learn about more COTS board options, or contact SLL on info@synaptic-labs.com for more information.