SLL's embedded software innovation has been recognised by our customers and partners. Major FPGA, memory, and development board makers now officially partner with SLL. This ensures SLL IP is validated on a wide range of physical devices. SLL customers are located in most geographical regions, and include Fortune Global 500's, government agencies, and SME's from USA and Canada to China.
xSPI Multiple Bus Memory Controller (xSPI-MBMC) IP v3
for HyperBus™ 1.0 and 2.0, OctaBus™, Xccela® Bus,
JEDEC® xSPI (JESD251) Profile 1.0 and Profile 2.0, …
FPGA and ASIC target support
SLL is Trenz Electronic’s partner
SLL is a Microchip (Microsemi) CompanionCore Partner
SLL is an Infineon Associated Partner
SLL is JSC’s partner
SLL collaborates closely with Macronix
SLL is Winbond’s partner
SLL is GigaDevice’s partner
SLL is a Microchip (Microsemi) CompanionCore Partner
SLL’s IP supports Xilinx FPGA devices
xSPI MBMC support for Commercial-off-the-shelf (COTS) boards
SLL has the broadest range of xSPI and xSPI-like board partners in this memory controller market. SLL has also tested our memory controller on the broadest range of COTS and proprietary boards in the market.
SLL leverages our close relationships to deliver known-working reference designs with trial copies of xSPI MBMC (that do not expire) to: (a) reduce your project risk; and (b) get you to market faster. SLL’s board partners include:
- Trenz Electronic GmbH
- Aries Embedded GmbH
- Devboards GmbH
- Intel Corporation (Intel PSG)
- Microsemi Corporation a wholly owned subsidiary of Microchip Technology Inc. (Microsemi)
SLL has also run our memory controller IP on boards from other board vendors such as:
xSPI MBMC v3 support for Intel FPGA
SLL’s Multiple Bus Memory Controller (xSPI-MBMC) has already been ported to, and physically qualified with, several Intel FPGA device families including:
- Cyclone IV, V, 10 LP, 10 GX FPGA
- Cyclone V SoC
- MAX 10
- Arria 10 and Arria 10 SoC
- Startix 10
- Contact us if you need support on another device family…
Features:
- Supports GUI configuration in Intel Platform Designer (QSYS)
- Quartus Prime Pro Edition 18, 19.1, …
- Quartus Prime Standard Edition 18.1, 19.1, …
- Quartus Prime Web Edition 18.1, 19.1, …
- Use selected xSPI NOR Flash devices as a configuration flash for Intel Cyclone 10 LP using legacy SPI mode (1S-1S-1S) and then access that xSPI NOR Flash device at high clock speeds in xSPI mode (8D-8D-8D)
- Advanced Dynamic Phase Alignment PHY under development for maximum pin mapping flexibility and higher performance for 3V devices
Memory channel clock speeds:
- Supports 180-to-200 MHz @ 1.8V on all Cyclone 10 LP devices
- Supports 180-to-200 MHz @ 1.8V on all MAX 10 devices
- Supports 140-to-150 MHz @ 1.8V on Cyclone V and Cyclone V SoC
- Supports 200 MHz @ 1.8v and 133 MHz @ 3.0v clock speeds on:
- All Cyclone 10 GX
- All Arria 10 and Arria 10 SoC.
- Stratix 10
xSPI MBMC v3 support for Microchip (Microsemi) FPGA
SLL’s Multiple Bus Memory Controller (xSPI-MBMC) has already been ported, and physically qualified with, Microchip PolarFire FPGA
SLL is Microchip (Microsemi)’s chosen memory controller vendor to support 1.8V HyperBus, OctaRAM and Xccela PSRAM devices at up to the full 200 MHz on Microchip PolarFire.
xSPI MBMC IP is complementary to PolarFire’s DDRx solutions:
- Supports GUI configuration in Libero
- Up to 19x less FPGA Logic Elements (LE) than x16 DDR3L controller
- Up to 5x less FPGA I/O pins than x16 DDR3L
- Up to 4x less FPGA I/O pins than x8 DDR3L
- RISC-V software performance on 8-bit PSRAM @ 200 MHz is highly competitive with 16-bit DDR3 @ 333 MHz
Contact us at info@synaptic-labs.com to enroll for the Beta under our Early Access Program.
xSPI MBMC v3 support for Xilinx FPGA
SLL’s Multiple Bus Memory Controller (xSPI-MBMC) has already been ported to, and physically qualified with, several Xilinx FPGA device families including:
- 7-Series FPGA
- Artix-7
- Kintex-7
- Virtex-7
- Zynq-7000
- Ultrascale+
- Zynq Ultrascale+
- Virtex Ultrascale+ (XCVU9P) to support ASIC development
Features:
- Supports GUI configuration in Xilinx Vivado, including:
- 2019.1, 2020.1, …
- Advanced Dynamic Phase Alignment PHY under development for maximum pin mapping flexibility and maximum performance for all 1.8V and 3V devices
xSPI MBMC v3 support for standard cell ASIC
SLL’s Multiple Bus Memory Controller (xSPI-MBMC) is currently being ported to standard cell ASIC in a process and foundry agnostic manner.
The xSPI-MBMC port for ASIC can be prototyped on all major FPGA platforms, with a particular focus on Virtex Ultrascale+ (XCVU9P) for system level prototyping.
Contact us at info@synaptic-labs.com to enrol for the Beta under our Early Access Program.
xSPI MBMC v3 support for Lattice FPGA
SLL can port our xSPI MBMC IP to many Lattice FPGA device variants, including:
- Lattice MachXO2 FPGA
- and other Lattice FPGA devices.
Please contact us on info@synaptic-labs.com for more information.
xSPI MBMC v3 support for Effinix FPGA
SLL can port our xSPI MBMC IP to support most Efinix Trion FPGA device variants.
Please contact us on info@synaptic-labs.com for more information.
Contact SLL for information on many development board options for all these memory vendors xSPI memory devices: info@synaptic-labs.com
