SLL's embedded software innovation has been recognised by our customers and partners. Major FPGA, memory, and development board makers now officially partner with SLL. This ensures SLL IP is validated on a wide range of physical devices. SLL customers are located in most geographical regions, and include Fortune Global 500's, government agencies, and SME's from USA and Canada to China.
Tiny Cache for On-Chip and Off-Chip Flash
SLL has a range of cache designs.
This Tiny Cache (T003) product is a high performance, write-through cache for on-chip and off-chip flash. It is also suitable for time analysable systems. This IP can actually REDUCE total project circuit area costs in some customer designs.
KEY FEATURES:
- up to 69x faster software performance when running from serial FLASH
- Intel Avalon compliant
- set-associative
- low-associativity, true LRU
- use as L1 and L2 flash cache
- tiny footprint: from only 27 ALM (~54 Logic Elements)
USE THIS TINY CACHE IP WITH THE FREE INTEL NIOS II / ECONOMY CORE
This IP can be used as a instruction and data cache for Nios II/e.
It makes the Nios II/e processor core more useful and performance much faster.
It can be used with serial off-chip and parallel on-chip flash.
USE THIS IP WITH THE INTEL NIOS II / FAST CORE ON MAX10 FPGA’S
Use Tiny Cache T003 to replace the Nios® II/f Flash Accelerator.
- lower circuit area
- many times higher performance
In particular, run the Nios II/f core in non-burst mode (to take advantage of the low circuit area of the Avalon Interconnect when used in non-burst mode) and use Tiny Cache T003 to significantly accelerate access to the MAX 10 User FLASH Memory (UFM) when compared to using the Nios II/f Flash Accelerator.
SLL has a range of cache designs that we can tailor to your specific project requirements.
For example, for accelerating SDRAM and HyperFlash in general purpose and real-time applications.
Contact us info@synaptic-labs.com for more information.
